← 返回 JSSC 论文列表
📄 下载 JSSC 原文 PDF
JSSC 2025第11期Analog Circuits65nm

A TDMA Neural Recording SoC With IIR-RLS Adaptive Filters for 83.4 dB Artifact Suppression Across 256 Channels

一款采用IIR-RLS自适应滤波器的TDMA神经记录SoC,实现83.4 dB刺激伪迹抑制
65nm CMOS, 4.9/4.8 µVrms噪声, 5.8 µW功耗
神经记录刺激伪迹抑制自适应滤波器TDMASoC
16电极TDMA方案
IIR-RLS自适应滤波器
实时伪迹抑制
Abstract
This article introduces a digitally-assisted, multi- electrode neural recording system equipped with a multi-channel stimulation artifact canceller (SAC) module. The system employs a 16-electrode time division multiple access (TDMA) scheme, allowing multiplexed neural signals to be recorded through a single shared analog front end (AFE). Simultaneously, it cancels stimulation artifacts from 16 stimulation electrodes using an infinite impulse response (IIR) recursive least squares (RLS) adaptive