JSSC 2025第11期Analog Circuits65nmNeural Interface

A TDMA Neural Recording SoC With IIR-RLS Adaptive Filters for 83.4 dB Artifact Suppression Across 256 Channels

一款采用IIR-RLS自适应滤波器的TDMA神经记录SoC，实现83.4 dB刺激伪迹抑制

65nm CMOS, 4.9/4.8 µVrms噪声, 5.8 µW功耗

神经记录刺激伪迹抑制自适应滤波器TDMASoC

▸创新点1：16电极TDMA方案（系统创新）。该方案通过时分复用技术，允许多个电极信号通过单一共享模拟前端（AFE）进行记录，显著减少了硬件复杂性和面积占用，同时提高了系统的可扩展性和资源利用率。

▸创新点2：IIR-RLS自适应滤波器（方法创新）。采用无限脉冲响应（IIR）递归最小二乘（RLS）自适应滤波器，实现了对16个刺激电极的伪迹实时抑制，具有快速收敛（<5.1 s）和高抑制能力（83.4 dB），显著提升了神经信号记录的准确性。

▸创新点3：实时伪迹抑制（系统创新）。该系统能够在体外实验中实时抑制100 mV的刺激伪迹，抑制能力高达83.4 dB，且对信号的信噪比和失真率（SNDR）影响极小（仅0.8 dB），确保了高质量的信号记录。

▸创新点4：能效与面积优化（电路创新）。采用65 nm工艺制造的SoC，每个记录电极AFE面积仅为0.0018 mm²，功耗低至5.8 µW，SAC模块功耗为2.9 µW/TF，实现了高性能与低功耗的平衡，适合大规模神经记录应用。

Abstract

This article introduces a digitally-assisted, multi- electrode neural recording system equipped with a multi-channel stimulation artifact canceller (SAC) module. The system employs a 16-electrode time division multiple access (TDMA) scheme, allowing multiplexed neural signals to be recorded through a single shared analog front end (AFE). Simultaneously, it cancels stimulation artifacts from 16 stimulation electrodes using an infinite impulse response (IIR) recursive least squares (RLS) adaptive filter (AF). The proposed system-on-chip (SoC) is validated in vitro, demonstrating an instantaneous, real-time sup- pression of 100 mV stimulation artifacts by 83.4 dB, with rapid AF calibration convergence times under 5.1 s for 256 channel transfer function (TF) combinations. Fabricated using a 65 nm process, each recording electrode AFE occupies 0.0018 mm 2, achieves an input-referred noise of 4.9/4.8 µVrms for local field potential (LFP) and action potential (AP) bands respectively, and consumes 5.8 µW in recording mode. The SAC module consumes 2.9 µW/TF and minimally impacts recording signal- to-noise and distortion ratio (SNDR) by 0.8 dB. This results in a high-performing SAC chip, optimized for energy and area efficiency.