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JSSC 2025第11期RF & Wireless22nm

Fully Analog, Multi-Lag, RF Correlators for Code-Domain Radars Using

提出一种全模拟、无乘法器的射频相关器,用于高能效雷达应用。
22nm SOI-CMOS, 4GS/s, 256×256相关, >8bit精度, 1000 1b-TOPS/W, 1.3 1b-TOPS/mm²
全模拟相关器射频相关器边际传播代码域雷达高能效
创新点1:采用分源跟随器架构(电路创新),通过独特的源极分割设计实现高效的信号采样与处理,显著降低功耗并提升信号完整性,支持4GS/s的高数据率。
创新点2:利用边际传播计算范式(方法创新),在采样域中实现非线性计算,无需传统乘法器即可完成高精度(>8bit)相关运算,能量效率达1000 1b-TOPS/W。
创新点3:紧凑的四晶体管计算单元设计(电路创新),仅用4个晶体管构建核心计算模块,面积效率达1.3 1b-TOPS/mm²,同时保持对PVT变化的鲁棒性。
创新点4:基于采样的长延迟实现技术(系统创新),采用创新的采样方法替代传统模拟延迟线,支持256点单次相关运算,实现全256×256交叉相关功能。
Abstract
We present a fully analog, multiplier-free, sampled- domain RF correlator to achieve high energy e fficiency for radar workloads. The RF correlator employs a split-source follower architecture that leverages the margin propagation (MP) computing paradigm in the sampled domain. As a proof of concept, we implement a 256 × 256 fully analog cross correlator in a 22 nm SOI-CMOS process. Large analog delays are realized using a sampling-based approach, and the design incorporates a compact, power and area-e fficient four-transistor compute cell. The fabricated IC achieves: 1) input and template data rates up to 4GS /s; 2) single-shot 256-point cross correlations across 256 lags, enabling full 256 × 256 cross correlation; 3) >8 bit compute accuracy; 4) energy e fficiency of 1000 1b-TOPS /W and 5) compute density of 1.3 1b-TOPS /mm2 per cell. The MP correlator demonstrates robust performance across process–voltage–temperature (PVT) variations and is deployed in a code-domain radar system with multi-user operation, validating system-level feasibility.