A 12.8-GS/s Time-Interleaved Sub-Sampling ADC Front End With 38-GHz Input Bandwidth and >39-dB SNDR for 1–32 GHz in 22-nm FDSOI

Abstract

In this article, we present a 4 × time-interleaved analog-to-digital converter (ADC) front end operating at 12.8 GS /s. We designed for a high tracking bandwidth (BW) of 38 GHz and optimized the SNDR up to the 5th Nyquist zone. This allows covering the targeted Ka-band frequencies of 27–31 GHz allocated for high-throughput Earth-to-satellite communication without the need for a dedicated mixer, enabling a wideband direct RF sub-sampling receiver approach. We employ an inductor-based input network together with co-optimized push–pull bu ffers and an active bootstrapping concept in the critical first track-and-hold (TH) for BW enhance- ment and improved linearity. Because the focus of this work lies in achieving a high SNDR at multi-ten-GHz inputs rather than maximizing the sampling rate f S, we implement a single 1st-rank TH to eliminate the need for skew and BW mismatch calibration. A prototype of this two-rank TH is implemented in 22-nm FDSOI technology. Measurements of four di fferent chip samples indicate SNDR >39 dB up to 32-GHz input fre- quency at 12.8-GS/s operation while consuming 87 mW. A sweep of f S from 4.8 to 15.2 GHz and ±10% supply variation causes <1.3-dB SNDR fluctuation at a 30.2-GHz input. We estimate the total aperture jitter to about 25 fs, and an input S11< −12dB is achieved up to 35 GHz.