A 4.6-GHz 54.5-fs rms PLL-XO Co-Design Featuring a Pulse-Injection XO Driver

Abstract

This article presents a power-e fficient and low-jitter frequency generation and synthesis architecture that leverages a phase-locked loop (PLL) and crystal oscillator (XO) co-design, integrated with a pulse-injection XO driver. The proposed co- design exploits the low-jitter and fine phase resolution of the PLL output to inject energy into the XO precisely at low-impulse- sensitivity-function (ISF) points, enhancing XO performance and subsequently reducing the in-band phase noise of the PLL. In addition, a low-kickback reference buffer is introduced, utilizing a cascoded transistor to mitigate buffer-induced switching kickback and further suppress bu ffer phase noise. Fabricated in a 22- nm FDSOI process, the prototype occupies an active area of 1.14 mm 2, with the pulse-injection driver consuming only 0.014 mm2. The measured integrated jitter from 1 kHz to 100 MHz is 54.5 fs rms at 4.6 GHz, while the reference and second harmonic spurs are −71 and −70.4 dBc, respectively. The complete system consumes 7.24 mW, including 1.92 mW for the pulse-injection driver, and achieves a jitter figure-of-merit (FoM) of −256.7 dB, capturing the combined contributions of the PLL, XO, and reference buffer.