A 72-GS/s 9b Time-Interleaved Pipeline-SAR ADC Achieving 55.3/49.3-dB SFDR at 20-GHz /Nyquist Inputs in 16-nm FinFET

Abstract

This article presents a 72-GS /s 9-bit time- interleaved (TI) pipeline-successive approximation register suc- cessive approximation register (SAR) analog-to-digital converter (ADC) that achieves a spurious-free dynamic range (SFDR) of over 55 dB at a 20-GHz input. The design features a hierarchical interleaver in conjunction with common-source- compensated source-follower bu ffers and fully split bootstrap switches. They enhance both the bandwidth and linearity of the TI-ADC for high-frequency (HF) inputs while alleviating bandwidth mismatches across channels. A resistor-over-resistor (R/R)-based residue amplifier (RA) and a common-mode voltage (VCM)-regulated switching scheme stabilize the inter-stage gain (ISG) in the unit pipeline-SAR ADC. The 72-GS /s prototype is fabricated using a 16-nm FinFET process and consumes 393.6 mW, excluding an off-chip TI mismatch calibration engine. It achieves a 46.4-dB signal-to-noise-and-distortion ratio (SNDR) and a 63.6-dB SFDR at a low-frequency (LF) input, while a 37.0-dB SNDR and 49.3-dB SFDR at a Nyquist input.