A 72-GS/s 9b Time-Interleaved Pipeline-SAR ADC Achieving 55.3/49.3-dB SFDR at 20-GHz /Nyquist Inputs in 16-nm FinFET

Abstract

This article presents a 72-GS /s 9-bit time- interleaved (TI) pipeline-successive approximation register suc- cessive approximation register (SAR) analog-to-digital converter (ADC) that achieves a spurious-free dynamic range (SFDR) of over 55 dB at a 20-GHz input. The design features a hierarchical interleaver in conjunction with common-source- compensated source-follower bu ffers and fully split bootstrap switches. They enhance both the bandwidth and linearity of the TI-ADC for high-frequency (H