A Calibration-Free Pipelined-SAR ADC With Cross-Stage Gain-Mismatch Error Shaping and Inherent Noise Shaping

Abstract

This article presents a calibration-free pipelined- successive-approximation-register (SAR) analog-to-digital converter (ADC) based on the proposed cross-stage gain- mismatch-error shaping (CS-GMES) mechanism. The CS-GMES is realized by including the entire 2nd stage into MES operation to unify the gain error and the 2nd-stage mismatch error. A feedback capacitor provides cross-stage connection and mismatch reference, and prevents saturation issues. Besides, low-cost noise shaping (NS) is achieved by the inherent residue preservation of the 2nd stage. A negative-R-assisted residue integrator instead of an amplifier is proposed to realize high-e fficiency residue summation and 1st-order error- feedback NS. With the proposed techniques, the prototype fabricated in a 55-nm CMOS process achieves a 93.3-dB signal-to-noise-and-distortion-ratio (SNDR) within a bandwidth of 156.25 kHz without any o ff-chip calibration. It consumes 306.88 uW from a 1.2-V supply and exhibits a 180.4-dB Schreier figure of merits (FoM). Among a gain error range of −33% to +50%, the SNDR drops less than 3 dB.