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JSSC 2025第12期Data Converters55nm

A Calibration-Free Pipelined-SAR ADC With Cross-Stage Gain-Mismatch Error Shaping and Inherent

提出一种无需校准的流水线-SAR ADC,采用跨级增益失配误差整形技术
55nm CMOS, 1.2V, 93.3dB SNDR, 156.25kHz带宽, 306.88uW功耗
ADC校准-free流水线-SAR增益失配噪声整形
跨级增益失配误差整形(CS-GMES)
负阻辅助残差积分器
低成本噪声整形(NS)
Abstract
This article presents a calibration-free pipelined- successive-approximation-register (SAR) analog-to-digital converter (ADC) based on the proposed cross-stage gain- mismatch-error shaping (CS-GMES) mechanism. The CS-GMES is realized by including the entire 2nd stage into MES operation to unify the gain error and the 2nd-stage mismatch error. A feedback capacitor provides cross-stage connection and mismatch reference, and prevents saturation issues. Besides, low-cost noise shaping (NS) is achiev