A Cryo-CMOS 800-MS /s 7-bit Charge-Injection SAR ADC With Only 4-fF Input Capacitance and 64-dB SFDR in 40-nm Bulk CMOS

Abstract

This article presents a cryogenic CMOS (cryo- CMOS) 800-MS /s 7-bit analog-to-digital converter (ADC) with an input capacitance of only 4 fF, which is >13× lower than the prior art. This small capacitance is enabled by its charge-injection digital-to-analog converter (CI-DAC), which maximally exploits the low thermal noise in the cryogenic environment. Despite its small input capacitance, this ADC maintains a high linearity by: 1) implementing a split CI-DAC with a bidirectional charge flow, which keeps the CI-DAC output common mode constant throughout the conversion; 2) by adopting a bottom-plate sam- pling scheme; and 3) by introducing a static preamplifier in the comparator. The resulting prototype ADC, implemented in a 40- nm bulk CMOS technology, has a core area of only 0.0056 mm 2 and a full-scale input swing of 0.84 Vpp,diff. It achieves an SNDR of 40.7 dB, an SFDR of 64.1 dB, and an e ffective resolution bandwidth (ERBW) of 2.5 GHz at a temperature of 6.5 K. It dissipates 2.89 mW at a sample rate of 800 MS /s.