A Filter-Embedded Pipe-SAR ADC With Progressive Conversion and Floating Charge Transfer Amplifier

Abstract

This article presents a filter-embedded pipelined successive-approximation (SAR) (pipe-SAR) analog-to-digital converter (ADC) architecture that achieves high e fficiency and wide bandwidth for next-generation wireless applications. A progressive conversion technique is proposed to improve the conversion speed of filter-embedded SAR ADCs by parallelizing the filtering and SAR quantization phases, which also pro- vides a more process–voltage–temperature (PVT)-robust and clock-scalable transfer function compared to active RC filters. Additionally, this article introduces floating charge transferrer (FCT), a novel dynamic high-speed open-loop residue amplifier that o ffers low design complexity, high power e fficiency, and inherent PVT robustness. Fabricated in a 28-nm CMOS process, the prototype filter-embedded ADC achieves 70.1-dB SNDR over an 80-MHz filter bandwidth while consuming only 4.9 mW of power, resulting in a Schreier figure of merit (FoM) of 172.2 dB. It provides over 30-dB out-of-band suppression for full-scale block- ers and more than 5× scalability in sampling rate and bandwidth, demonstrating its potential to substitute continuous-time delta- sigma modulators (CT-DSMs) in advanced wireless receivers.