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A Fractional-N Cascaded PLL With MMD-Based Quantization-Error Cancellation
提出一种基于MMD量化误差消除的级联分数-N锁相环，有效抑制量化噪声和带内分数杂散。
65nm CMOS, 82 MHz参考频率, 96 fs RMS抖动, -70.6 dBc带内分数杂散, 21.2 mW功耗, FoM -247.1 dB
分数-N锁相环级联架构多模分频器量化误差消除Δ-Σ调制器
▸创新点1：引入辅助多模分频器（MMD）作为级联PLL架构的核心创新，通过在第一级整数N PLL和第二级分数N PLL之间插入辅助MMD，实现了量化误差的同步生成与抵消，显著降低了整体相位噪声（系统创新）
▸创新点2：共享Δ-Σ调制器（DSM）设计，使辅助MMD与主MMD共用同一调制器，确保两路径量化误差高度一致，通过数学推导证明误差抵消因子可达N倍（电路创新）
▸创新点3：提出无校准量化噪声消除技术，实测显示82MHz参考时钟下RMS抖动仅96fs，带内分数杂散抑制达-70.6dBc，FoM指标-247.1dB创纪录（性能创新）
▸创新点4：创新性地利用PD非线性产生的带内分数杂散与量化噪声的关联特性，通过误差抵消机制同步抑制两类干扰（方法创新）
Abstract
A fractional-N phase-locked loop (PLL) with cas- caded architecture is presented. Compared to the conventional cascaded PLL, an auxiliary multi-modulus divider (MMD) is added between the first-stage integer-N PLL and the second-stage fractional-N PLL. This auxiliary MMD shares the same delta- sigma modulator (DSM) with the main MMD in the second-stage loop. Analysis shows that the two quantization errors (Q-errors) at the auxiliary and main MMD outputs are nearly identical, and the overall Q-error is canceled by a factor of N. A proof-of- concept prototype is implemented in 65-nm CMOS technology, and the e ffectiveness of the proposed technique is demonstrated through measurement results, where both the quantization noise (Q-noise) and the in-band fractional spurs arising from the PD nonlinearity are e ffectively suppressed. With an 82 MHz reference, the PLL achieves 96 fs RMS jitter and −70.6 dBc worst-case in-band fractional spur while consuming 21.2 mW, leading to a FoM of −247.1 dB, without any calibration.