A Fractional-N Cascaded PLL With MMD-Based Quantization-Error Cancellation

Abstract

A fractional-N phase-locked loop (PLL) with cas- caded architecture is presented. Compared to the conventional cascaded PLL, an auxiliary multi-modulus divider (MMD) is added between the first-stage integer-N PLL and the second-stage fractional-N PLL. This auxiliary MMD shares the same delta- sigma modulator (DSM) with the main MMD in the second-stage loop. Analysis shows that the two quantization errors (Q-errors) at the auxiliary and main MMD outputs are nearly identical, and the overall Q-erro