JSSC 2025第12期Clocking & PLLs40nm

A Low-Jitter Fractional- N Digital PLL Using a Quantization-Error-Compensating B

提出一种采用量化误差补偿技术的低抖动分数-N数字锁相环

40nm CMOS, 14.4mW, 64fs rms抖动, -62.8dBc杂散

分数-N锁相环量化误差补偿Bang-Bang相位检测器正交多项式校准低抖动

▸量化误差补偿Bang-Bang相位检测器(QEC-BBPD)

▸正交多项式最小均方多变量校准(OP-LMS MVC)

▸降低ΔΣ调制器量化误差的动态延迟和静态延迟

Abstract

This work presents a 10.0–11.5-GHz fractional- N digital phase-locked loop (DPLL) using the quantization-error- compensating bang–bang phase detector (QEC-BBPD) that can minimize both the static delay ( TS) and the dynamic delay ( TD) required for removing the delta-sigma modulator’s (∆ΣM) quantization-error (Q-error). Since the proposed QEC- BBPD reduces additional thermal noise during the Q-error- compensation process, it allows the DPLL to achieve low in-band phase noise (PN) and low rms jitt