← 返回 JSSC 论文列表JSSC 2025第12期Clocking & PLLs28nmPLL
A Low-Noise Digital PLL With an Adaptive Common-Mode Resonance Tuning Technique for V oltage-Biased Oscillators
提出一种采用自适应共模谐振调谐技术的低噪声数字PLL，优化相位噪声性能。
45.9 fs抖动，-257 dB功率-抖动优值，-146.6 dBc/Hz @10MHz偏移，4.75GHz载波
数字锁相环共模谐振调谐相位噪声压控振荡器CMOS
▸自适应共模谐振调谐技术：该方法通过动态调整共模谐振点以最小化相位噪声，实现了背景连续调谐，无需中断系统操作。其创新性在于利用注入信号的频率敏感性作为反馈机制，自动优化谐振状态，显著提升了相位噪声性能（实测-146.6 dBc/Hz @10MHz）。
▸基于灵敏度检测的谐振优化：通过向交叉耦合晶体管栅极注入dither信号并监测振荡器频率的敏感性变化，提出了一种新颖的谐振点检测方法。当敏感性趋近零时，系统判定达到最优谐振状态，此方法创新性地将传统开环调谐转化为闭环自适应控制。
▸数字PLL系统架构创新：整合自适应调谐模块与数字控制振荡器（DCO），在28nm CMOS工艺下实现45.9 fs超低抖动性能，其功耗-抖动品质因数（FoM）达-257 dB，系统级创新体现在将谐振优化与PLL核心功能无缝协同。
▸全调谐范围背景操作：突破性地实现整个调谐范围内的实时自适应调整，克服了传统技术需中断校准的局限。该电路创新通过数字控制逻辑与模拟检测电路的混合设计，确保调谐过程不影响PLL正常工作时序。
Abstract
This work presents a digital phase-locked loop (PLL) incorporating an adaptive common-mode (CM) resonance tuning technique applied to a voltage-biased digitally-controlled oscillator (DCO). The method leverages the principle that the sensitivity of the oscillator frequency to a dither signal injected into the gate voltage of the cross-coupled transistors diminishes to near zero when the CM resonance is optimally tuned for minimal phase noise (PN). By detecting and nullifying this sensitivity, the proposed technique automatically adjusts the CM resonance to its ideal value. This background operation is continuous across the entire tuning range. The concept was validated through a digital PLL prototype fabricated in a 28-nm CMOS process, which achieved a jitter of 45.9 fs, a power-versus-jitter figure-of- merit of −257 dB, and a PN of −146.6 dBc/Hz at 10-MHz o ffset from a 4.75-GHz carrier, all within an active area of 0.21 mm 2.