A Low-Noise Digital PLL With an Adaptive Common-Mode Resonance Tuning Technique for V oltage-Biased Oscillators

Abstract

This work presents a digital phase-locked loop (PLL) incorporating an adaptive common-mode (CM) resonance tuning technique applied to a voltage-biased digitally-controlled oscillator (DCO). The method leverages the principle that the sensitivity of the oscillator frequency to a dither signal injected into the gate voltage of the cross-coupled transistors diminishes to near zero when the CM resonance is optimally tuned for minimal phase noise (PN). By detecting and nullifying this sensitivity, th