ISSCC 2008
Session 3
Other
A Gain-Boosted Discrete-Time Charge-Domain FIR LPF with Double-Complementary MOS Parametric Amplifiers
Discrete-time charge-domain filters with FIR characteristics [1,2] require the resetting of their sampling capacitors for every cycle. However, since this resetting operation attenuates the signal when charge sharing is
ISSCC 2008
Session 3
Other
A Continuous-Time Hexagonal Field-Programmable Analog Array in 0.13µm CMOS with 186MHz GBW
The high non-recurring engineering costs of integrated circuit design make rapid-prototyping an important field of microelectronics. For digital circuits, FPGAs are highly developed and have become indispensable as both
ISSCC 2008
Session 3
Other
A 6th-Order 100µA 280MHz Source-Follower-Based Single-loop Continuous-Time Filter
The source follower is a well known basic building block for CMOS design. A capacitively loaded source follower acts as a 1st-order lowpass filter and exhibits excellent linearity, especially with reduced overdrive volta
ISSCC 2008
Session 3
Other
A Current-Feedback Instrumentation Amplifier with 5µV Offset for Bidirectional High-Side CurrentSensing
For power management in mobile systems, the supply current is often measured through a small sense resistor in series with the positive power supply. The voltage across this high-side sense resistor is then amplified and
ISSCC 2008
Session 3
Other
A BiCMOS Operational Amplifier Achieving 0.33µV/°C Offset Drift using Room-Temperature Trimming
Johan H. Huijsing1, Kofi A. A. Makinwa1 Delft University of Technology, Delft, Netherlands National Semiconductor, Delft, Netherlands A detailed circuit diagram of the input stage is shown in Fig. 3.6.2. The PTAT trimmin
ISSCC 2008
Session 3
Other
130dB-DR Transimpedance Amplifier with Monotonic Logarithmic Compression and HighCurrent Monitor D. Micušík, H. Zimmermann ˇ
signal. This is especially a problem for optical sensing applications, in which the input photocurrent usually has a very wide dynamic range (DR). Various methods have been developed to overcome this limitation [1-4]. Th
ISSCC 2008
Session 30
Data Converters
An Over-60dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp with 30dB Loop Gain
Finite opamp gain and output swing are two limitations for precision analog circuits. These limitations are especially serious at lower supply voltages where limited headroom prevents the use of cascode devices to improv
ISSCC 2008
Session 30
Data Converters
A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13µm CMOS
widely used in serial links, magnetic recording systems and UWB receivers. Flash ADCs have been dominantly used for these applications. This paper presents an ADC that takes advantage of the high-speed digital logic and
ISSCC 2008
Session 30
Data Converters
A 24GS/s 6b ADC in 90nm CMOS
Robert Gibbins1, Yuriy Greshishchev1, Naim Ben-Hamida1, Daniel Pollex1, John Sitch1, Shing-Chi Wang1, John Wolczanski1 1 Nortel, Ottawa, Canada STMicroelectronics, Crolles, France 2 New receivers for 10-to-40Gb/s optical
ISSCC 2008
Session 30
Data Converters
A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS
demand high-resolution high-speed low-voltage ADCs. Pipelined ADCs are well suited for these applications. However, traditional designs of such high-resolution ADCs rely on high-gain operational amplifiers along with goo
ISSCC 2008
Session 30
Data Converters
90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with OnChip Characterization
Infineon Technologies, Munich, Germany Technical University Munich, Munich, Germany 2 Time-to-digital converters (TDC) support the industry wide trend of replacing mixed-signal functionality by digital realizations. High
ISSCC 2008
Session 30
Data Converters
A Clockless ADC/DSP/DAC System with ActivityDependent Power Dissipation and No Aliasing
The fixed sampling and clock rates in conventional DSPs result in power dissipation determined by the highest frequency to be processed. If sampling and clock are eliminated, one has a DSP operating in continuous-time [1
ISSCC 2008
Session 30
Data Converters
A Split-Load Interpolation-Amplifier-Array 300MS/s 8b Subranging ADC in 90nm CMOS
Subranging ADCs meet these requirements by using simple open-loop amplifiers [1, 2]. However, the large number of parallel connected differential amplifiers (pre-amps) and comparators create a bottleneck, making it diffi
ISSCC 2008
Session 30
Data Converters
A 6b 0.2-to-0.9V Highly Digital Flash ADC with Comparator Redundancy
Microsensor wireless networks and implanted biomedical devices have emerged as exciting new application domains. These applications are highly energy constrained and require flexible, integrated, energy-efficient ADC mod
ISSCC 2008
Session 31
RF & Wireless
TX and RX Front-Ends for 60GHz Band in 90nm Standard Bulk CMOS CMOS PA performance even at a low drain voltage of 1.0V or less [3, 4, 7].
Masaharu Ito2, Naoyuki Orihashi2, Kenichi Maruhashi2, Hidenori Shimawaki1 The block diagrams of the transmitter and receiver front-ends are shown in Fig. 31.1.4. The direct-conversion configuration is adopted for chip mi
ISSCC 2008
Session 31
AI / ML
A 60GHz 1V +12.3dBm Transformer-Coupled Wideband PA in 90nm CMOS
The opening up of the mm-wave band has created opportunities for high-data-rate communication, radar and medical imaging. The cost and size advantages of CMOS have motivated research on 60GHz CMOS front-end design [1]. H
ISSCC 2008
Session 31
RF & Wireless
60 and 77GHz Power Amplifiers in Standard 90nm CMOS
frequency mm-wave applications such as short-range communications (60GHz band) [1, 2] and automotive radar (77GHz band) [3]. The power amplifier (PA) is one of the most challenging blocks in the transmitter due to the lo
ISSCC 2008
Session 31
RF & Wireless
A Single-Chip WCDMA Envelope Reconstruction LDMOS PA with 130MHz Switched-Mode Power Supply
signals and generally use low-efficiency linear power amplifiers. Envelope reconstruction (ER) polar architecture allows linear amplification with high efficiency, since the RF phase signal is amplified by a saturated PA
ISSCC 2008
Session 31
RF & Wireless
A 28.6dBm 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation
near-watt-level output power in nanometer CMOS is difficult to satisfy owing to the power supply voltage scaling with minimum feature size. High performance is problematic because most PA interfaces are defined by a 50Ω
ISSCC 2008
Session 31
RF & Wireless
An Outphasing Power Amplifier for a SoftwareDefined Radio Transmitter
transmitter needs a universal modulator and power amplifier to support any modulation in any band. There is a simple solution, namely, a Cartesian I-Q upconverter followed by a linear power amplifier, but for complex mod
ISSCC 2008
Session 31
RF & Wireless
A Fully Integrated Quad-Band GSM/GPRS CMOS Power Amplifier
G. Hatcher, D. McClymont, A. Hajimiri Axiom Microdevices, Irvine, CA There is a strong drive toward handheld communication devices with building blocks that are fully integrated in standard CMOS technologies. Although th
ISSCC 2008
Session 31
RF & Wireless
Balanced SiGe PA Module for Multi-Band and Multi-Mode Cellular-Phone Applications
STMicroelectronics, Catania, Italy Rapidly expanding market for multi-mode (MM) and multi-band (MB) cellular phones has recently fueled the demand for RF Power Amplifiers (PAs) that are able to operate with 2G, 2.5G and
ISSCC 2008
Session 32
Sensors
A CMOS Temperature-to-Digital Converter with an Inaccuracy of ±0.5°C (3σ) from –55 to 125°C
This paper describes a CMOS temperature-to-digital converter (TDC) based on thermal diffusivity sensing, which is an interesting alternative to conventional band-gap temperature sensors because the thermal diffusivity of
ISSCC 2008
Session 32
Sensors
A 1.5μW 1V 2nd-Order ΔΣ Sensor Front-End with Signal Boosting and Offset Compensation for a Capacitive 3-Axis Micro-Accelerometer
current and the capability of achieving high sensitivity, are emphasized in ultra-low-power applications. In [1], representing the current state-of-the-art in low-power 3-axis micro-accelerometers, capacitance-to-voltage
ISSCC 2008
Session 32
Sensors
A Mode-Matching ΔΣ Closed-Loop VibratoryGyroscope Readout Interface with a 0.004°/s/√Hz Noise Floor over a 50Hz Band
floors, mode matching is necessary to moderate interface power dissipation. Mode matching increases sense displacements by the sense mode quality factor and thereby relaxes the precision requirements of the front-end, bu
ISSCC 2008
Session 32
Sensors
An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation IBA, no failure is observed up to 1.7×108 cycles, indicating that the charging suppression mechanism is working successfully.
Etsuji Ogawa, Shinji Miyano, Tomohiro Saito, Tatsuya Ohguro, Takeshi Miyagi, Yoshiaki Sugizaki, Nobuaki Otsuka, Hideki Shibata, Yoshiaki Toyoshima The IBA operation described above is realized by a circuit whose block di
ISSCC 2008
Session 32
Sensors
A Chopper-Stabilized Lateral-BJT-Input Interface in 0.6µm CMOS for Capacitive Accelerometers
There has been increasing demand for low-cost small-size highprecision MEMS accelerometers with micro-gravity resolution at very low frequencies in applications ranging from GPS-augmented inertial navigation to distance
ISSCC 2008
Session 32
Sensors
Single-Chip CMOS Analog Sensor-Conditioning ICs with Integrated Electrically-Adjustable Passive Resistors
integration of sensors and/or MEMS with ICs for many purposes, including enhancing the performance of the ICs [1]. Post-packaging or post-assembly in-system adjustment of analog circuits is increasing in industrial impor
ISSCC 2008
Session 32
Sensors
A 100µW 64×128-Pixel Contrast-Based Asynchronous Binary Vision Sensor for Wireless Sensor Networks
Raster-scan architectures are mostly oriented toward quality image reproduction [1], but they do not meet some basic requirements,that are crucial for battery-operated sensors for sensor network applications, such as low
ISSCC 2008
Session 32
Sensors
A 16×16 CMOS Proton Camera Array for Direct Extracellular Imaging of Hydrogen-Ion Activity
Over the past twenty-five years, silicon CMOS technology has firmly established itself as the dominant platform in the microelectronics industry. This has resulted in many recent initiatives to fabricate CMOS-based micro
ISSCC 2008
Session 4
Digital Processors
A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® Processor
Sun Microsystems, Santa Clara, CA The goals for this high-end commercial microprocessor are high throughput and high single-thread performance, mainframe-class reliability, hardware transactional memory, and linear scala
ISSCC 2008
Session 4
Digital Processors
Implementation of a Third-Generation 16-Core 32Thread Chip-Multithreading SPARC® Processor
Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar Sun Microsystems, Santa Clara, CA This third-generation chip-multithreadin
ISSCC 2008
Session 4
Digital Processors
Migration of Cell Broadband EngineTM from 65nm SOI to 45nm SOI
S. R. Cottier1, P. Coulman1, J. Culp3, G. Gervais1, M. S. Gray4, Y. Itaka5, C. J. Johnson2, F. Kono5, L. Maurice1, K. W. McCullen4, L. Nguyen1, Y. Nishino6, H. Noro5, J. Pille7, M. Riley1, M. Shen1, C. Takano6, S. Tokito
ISSCC 2008
Session 4
Digital Processors
TILE64TM Processor: A 64-Core SoC with Mesh Interconnect
Vince Leung, John MacKay, Mike Reif, Liewei Bao, John Brown, Matthew Mattina, Chyi-Chang Miao, Carl Ramey, David Wentzlaff, Walker Anderson, Ethan Berger, Nat Fairbanks, Durlov Khan, Froilan Montenegro, Jay Stickney, Joh
ISSCC 2008
Session 4
Digital Processors
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler
Tomoichi Hayashi1, Osamu Nishii1, Yoshihiko Yasu1, Atsushi Hasegawa1, Masashi Takada2, Masaki Ito2, Hiroyuki Mizuno2, Kunio Uchiyama2, Toshihiko Odaka2, Jun Shirako3, Masayoshi Mase3, Keiji Kimura3, Hironori Kasahara3 1
ISSCC 2008
Session 4
Digital Processors
A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor
The processor has 4 dual-threaded cores integrated on die with a system interface and 30MB of cache in an 8M 65nm process. The 21.5×32.5mm2 die contains 2.05 billion transistors (Fig. 4.6.1). The silicon is designed to o
ISSCC 2008
Session 4
Digital Processors
Circuit Design for Voltage Scaling and SER Immunity on a Quad-Core Itanium® Processor
cores over its predecessor [2], from 2 to 4. It also adds a system interface that is roughly as large as two cores, including six QuickPath interconnects and four FBDIMM channels. This 3× increase in logic circuits per s
ISSCC 2008
Session 5
Wireline I/O
An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane
T. Takemoto1, T. Saito1, N. Chujo2, K. Yamamoto2, H. Kanai2, A. Hayashi1 1 Hitachi, Tokyo, Japan, 2Hitachi, Kanagawa, Japan IT systems such as servers and routers need high-speed lowerpower area-efficient chip-to-chip in
ISSCC 2008
Session 5
Wireline I/O
A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR
Modern broadband communication systems require high-speed receivers to process serial data at tens of gigabits per second. As the data rate reaches 40Gb/s, skin-effect and dielectric loss in the transmission medium cause
ISSCC 2008
Session 5
Wireline I/O
A 20Gb/s Duobinary Transceiver in 90nm CMOS
The ever growing volume of backplane communications pushes the data rate toward 20Gb/s for the next-generation transceivers. Over the years, chip designers have been seeking different data formats to overcome the loss of
ISSCC 2008
Session 5
Wireline I/O
A 6Gb/s RX Equalizer Adapted Using Direct Measurement of the Equalizer Output Amplitude
are the main challenges for robust communication. Reflection in transmission line (T-line) can be reduced by proper Tline design. But ISI stems from LPF characteristics of the actual Tline and becomes severe as either th
ISSCC 2008
Session 5
Wireline I/O
A 10Gb/s IEEE 802.3an-Compliant Ethernet Transceiver for 100m UTP Cable in 0.13µm CMOS stringent specification of >60dB linearity over the frequency band of 1 to 400MHz on the combined output of TXDAC, ECDAC and the subtraction circuit within the PGA.
Vishnu Balan, Michael Inerfield, Dariush Dabiri, John Dring, Sachin Goel, Kumaraguru Muthukumaraswamy, Frank McCarthy, Glenn Golden, Jiangfeng Wu, Susan Arno, Sanjay Kasturia The architecture for both the TX and EC DAC i
ISSCC 2008
Session 5
Wireline I/O
A Serial Data Transmitter for Multiple 10Gb/s Communication Standards in 0.13µm CMOS
Aeluros, Mountain View, CA The demand for higher speed and port densities in data networks has resulted in multiple 10Gb/s serial communication standards. For optical networks, this demand has spurred the development of
ISSCC 2008
Session 5
Wireline I/O
5. 7 A T-Coil-Enhanced 8.5Gb/s High-Swing SourceSeries-Terminated Transmitter in 65nm Bulk CMOS
the advantage of providing a large range of termination voltages, making them particularly suitable for multi-standard I/Os [1, 2]. Many standards (e.g. [3]) however, call for larger vertical eye openings that require ra
ISSCC 2008
Session 5
Wireline I/O
A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration
2Gb/s single-ended current-integrating DFE receiver with 8b parallel data for 2-drop DRAM interface is implemented in a 0.18µm CMOS process. The reference voltage for the receiver is generated internally to reduce the ex
ISSCC 2008
Session 6
RF & Wireless
A 1.8Gpulses/s UWB Transmitter in 90nm CMOS
The potential of pulse-based ultra-wideband (UWB) technology has been demonstrated for high-data-rate short-distance wireless personal area networks (e.g., wireless USB) [1-3]. With the allocation of the spectrum from 3.
ISSCC 2008
Session 6
RF & Wireless
A 0.18µm CMOS 802.15.4a UWB Transceiver for Communication and Localization
15.4a has specified a UWB PHY for low-rate commutation with ranging capability for wireless personnel area and sensor network applications [1]. Related work is reported on low-rate energy-efficient UWB radios [2-4]. Howe
ISSCC 2008
Session 6
RF & Wireless
A CMOS UWB Camera with 7×7 Simultaneous Active Pixels
Ultra-wideband (UWB) imaging systems achieve high depth resolution. UWB timed arrays use a collection of spaced antennas to achieve azimuth selectivity as well [1]. The recent trend in realization of integrated beam-form
ISSCC 2008
Session 6
RF & Wireless
A Fully Integrated 14-Band 3.1-to-10.6GHz 0.13µm SiGe BiCMOS UWB RF Transceiver
Y. Jin, J. Marcincavage Alereon, Austin, TX UWB is an emerging wireless technology supporting data rates as high as 480Mb/s. The US allows the deployment of UWB systems in the frequency band from 3.1 to 10.6GHz, while ot
ISSCC 2008
Session 6
RF & Wireless
UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking
high-data-rate WiMedia UWB systems is to design an efficient LO generation. On one hand, it must fulfill the stringent requirements (multiple LO frequencies, spurious, settling time and I/Q imbalance), and on the other h