2008

Donze1, Meenatchi Jagasivamani2, Egidio Buda1, Fabio Pellizzer1, David Chow2, Alessandro Cabrini4, Giacomo Matteo Angelo Calvi4, Roberto Faravelli4, Andrea Fantini4, Guido Torelli4, Duane Mills2, Roberto Gastaldi1, Giuli

Koji Hosono1, Masahiro Yoshihara1, Toru Miwa2, Yosuke Kato2, Alex Mak3, Siu Lung Chan3, Frank Tsai3, Raul Cernea3, Binh Le3, Eiichi Makino1, Takashi Taira1, Hiroyuki Otake1, Norifumi Kajimura1, Susumu Fujimura1, Yoshiaki

A versatile low-power headphone driver that can be used in a variety of portable electronic devices is desirable for compatibility and to reduce design-cycle time. Capacitive loads as large as 20nF are used in some platf

levels at high efficiencies, Class-D amplifiers are extremely attractive for systems-on-chip in mobile and low-power applications, where battery life and reduced thermal dissipation are crucial parameters. One modificati

circuits like analog-to-digital converters, voltage regulators, DRAMs, flash memories and other communication devices. The demands for smaller area, lower power consumption, and lower sensitivity to changes in supply vol

In order to be useful for mobile systems, the switching frequencies of modern buck converters (BCs) are in the MHz- or even GHzrange to enable the use of compact off-chip inductors and capacitors [1], or even on-chip Ls

Portable applications often need multiple voltages controlled by a power management IC to power up many functional blocks [1]. A switching pre-regulator is usually followed by a low dropout (LDO) regulator to provide a r

T. Peltola2, T. Teppo2 1 University of Pavia, Pavia, Italy National Semiconductor, Oulu, Finland 2 Minimizing power consumption in multi-processor systems requires the use of multiple supplies with a wide range of regula

KAIST, Daejeon, Korea JDA Technology, Daejeon, Korea 3 LG Electronics, Pyungtaek, Korea 2 Previously reported switching DC-DC converters have feedback loops incorporating error amplifiers to regulate their output voltage

Polar modulation has been proven to be an effective way to build high-efficiency high-linearity power amplifier systems [1]. In a polar transmitter, high-efficiency non-linear power amplifiers can be used for linearly mo

James E. Jaussi1, Joseph Kennedy1, Bryan Casper1, David J. Allstot2, Randy Mooney1 Intel, Hillsboro, OR, 2University of Washington, Seattle, WA 1 With the rise in aggregate bandwidth of microprocessors, there is an ever-

of phase noise because they have significantly less jitter accumulation [1,2,3]. Figure 25.2.1 shows the basic PLL and recirculating DLL. In the latter, the oscillator loop is periodically opened to let in a “clean” refe

NTT, Atsugi, Japan Gunma University, Kiryu, Japan 2 The data-timing generator (DTG) presented herein provides a delay of over 20× of the 10Gb/s data cycle, and operates over the wide frequency range of DC to 11Gb/s. The

Sergey V. Rylov1, Daniel J. Friedman1 1 IBM T.J. Watson, Yorktown Heights, NY IBM, Austin, TX 2 Quadrature-phase clock generation is required for many applications in wireless and wireline communications. Traditional clo

As an essential clock-system component, millimeter-wave dividers have been implemented for V- and W-band channels [1-8]. This has also served as a standard benchmark vehicle that reveals highspeed and low-power performan

Carlos Carvalho, Reza Yousefi, Muhammad Ali Khan, Trevor Monson, Mark Ayoub, Claus Reitlingshoefer Diablo Technologies, Gatineau, Canada Bandwidth and capacity of memory systems based on commodity DIMM are limited by the

Seyed Danesh1,3, Robert Henderson3, William Holland1, Jed Hurwitz1, Steve Maughan3, Alasdair Sutherland1, Ewan Watt1 Gigle Semiconductor, Edinburgh, United Kingdom, Gigle Semiconductor, Barcelona, Spain, 3 University of

The frequency divider (FD) [1,2] is one of the key components in very-high-frequency (VHF) PLLs. Conventionally, injection-locked frequency divider (ILFD) [3], Miller frequency divider [4], and CML static divider are wid

high-performance computing systems that enable high-throughput CPUto-CPU and CPU-to-memory data transfers. Slower wide-bus interfaces have been replaced by a narrower collection of higherspeed serial links (e.g., FBDIMM

David B. Tanner1, Chih-Ming Hung3, Kenneth K. O1 1 Univeristy of Florida, Gainesville, FL, 2NXP Semiconductors, Austin, TX Texas Instruments, Dallas, TX 3 The uses of terahertz systems (300GHz to 3THz) in radars, remote

properties; yet, a differential CMOS Colpitts oscillator, directly derived from a singled-ended topology, did not show a better phase noise performance than the conventional CMOS differential-pair LC-tank oscillator, not

University of California, Los Angeles, CA Jet Propulsion Laboratory, Pasadena, CA 3 Texas Instruments, Dallas, TX 2 Terahertz image and spectroscopic systems (operating in frequency range from 300GHz to 3THz) have drawn

Christophe Billard, Christine Fuchs, Guy Parat, Emeric Defoucaud, Alexandre Reinhardt CEA-LETI-MINATEC, Grenoble, France The frequency stability of integrated oscillators has become an increasingly important issue for th

millimeter-wave frequency operation have been reported recently [1-3]. Potential applications for such silicon ICs include: Gb/s communication (e.g., 60 and 120GHz bands), long-range collision avoidance radar for automob

Increasing demands for multi-Gb/s data transmission make the mm-wave wireless communication systems more attractive. The VCO is an essential block in these systems. This paper describes an amplitude-redistribution techni

making mmwave technology attractive for multi-Gb/s consumer-market applications. A key building block of the mm-wave transceiver is the frequency synthesizer. In this paper, we present a 39.1-to-41.6GHz 1.2V 64mW ΔΣ frac

use 2-level (+1, -1) unit elements in either switched-capacitor or current-steering form. This paper presents a low-power audio DAC that uses a 3-level current-steering unit element architecture. When compared to the 2-l

Low-voltage low-power ΔΣ modulators are required for many portable systems. Although SC ΔΣ modulators provide reliable high-resolution A/D conversion, the traditional SC circuit design faces many challenges as the fabric

Feature-size scaling [1] of modern CMOS technologies dictated by Moore’s law enables integration of extensive digital signal processing at low power consumption and small area. As the area of digital functions scales wit

Kaoru Takasuka2, Seiji Takeuchi2, Gabor C. Temes1 1 Oregon State University, Corvallis, OR, 2Asahi Kasei, Atsugi, Japan Wideband high-resolution ΔΣ ADCs with low power consumption are needed in many wired and wireless co

11n/WiMAX receivers (20 to 2.5MHz per I/Q) is presented. The intent is to replace complex analog baseband circuits with a combination of tunable one-pole filter, anti-alias filter and coarse VGA (Fig. 27.5.1) [1]. Blocke

bandwidth and high dynamic range. In such systems, a pipeline ADC requires a low-noise high-speed input buffer to drive the sampling capacitor and a sophisticated anti-aliasing filter whereas a CT ΔΣ ADC has an easy-to-d

University of California, San Diego, CA Conexant, Palm Bay, FL 2 In the digital wireless SoC applications, CT ΔΣ ADCs have been widely used for I/Q quantization due to the built-in anti-aliasing function and insensitivit

accomplished at the cost of analog design features. The prediction of the ITRS roadmap [1] shows a dramatic increase of flicker noise in new technologies. On the other hand, the voltage supply is reduced to almost 1V. Th

Tapan Samaddar1, Hao Nguyen1, Man Mui1, Khin Htoo1, Teruhiko Kamei1, Masaaki Higashitani1, Emilio Yero1, Gyuwan Kwon1, Phil Kliza1, Jun Wan1, Tetsuya Kaneko2, Hiroshi Maejima2, Hitoshi Shiga2, Makoto Hamada2, Norihiro Fu

Kohei Hashimoto, Tsukasa Oishi, Naoki Tsuji, Kiyohiko Sakakibara, Kenji Noguchi Figure 28.2.5 shows a software-leveling scheme with background operation (BGO) between a 512kB code Flash (with 50MHz highspeed page read mo

Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jaehoon Jang, Han-Soo Kim, Soon-Moon Jung, Yeong-Taek Lee, Changhyun Kim and Won-Seong Lee Samsung, Hwasung, Korea Recently, 3-dimensional (3-D) memories have regained attention

Junction, VT which results in a good balance between voltage ripple (affects power savings and skew/jitter improvement) and time to reach steady state (affects startup and low-frequency operation). The purpose of the fri

A conventional DLL employs a phase detector (PD), a charge pump, and a loop filter to compare and adjust the phase difference between the reference clock and the delayed clock. Ideally, when the DLL is locked, the delay

H. A. Ainspan1, D. Friedman1 1 IBM T.J. Watson, Yorktown Heights, NY Texas A&M University, College Station, TX 2 Digital phase-lock loop (DPLL) design approaches offer multiple advantages, including compactness, broad pr

multi-GHz microprocessors because the skew and jitter are proportional to the large latency in the conventional tree structure. A number of resonant techniques have been reported to overcome clock distribution problems [

currently prevent the seamless integration of wireless and networking capability into any tiny high-tech object such as hearing aids or miniature drug delivery monitoring devices or implants. The combination of MEMS tech

A wake-up receiver (WuRx) is used in wireless sensor networks (WSN) to detect wireless traffic directed to a node’s receiver and activate it upon detection, improving network latency and energy dissipation by maximizing

Jungki Choi3, Kihong Kim3, Jungsuk Lee3, Kyutae Lim1, Chang-Ho Lee2, Haksun Kim3,4, Joy Laskar1 1 Georgia Institute of Technology, Atlanta, GA Samsung RFIC Design Center, Atlanta, GA 3 Samsung Electro-Mechanics, Suwon, K

V. De Heyn, S. Thijs, D. Linten, G. Van der Plas, B. Parvais, M. Dehan, S. Decoutere, C. Soens, N. Collaert, M. Jurczak IMEC, Heverlee, Belgium CMOS scaling beyond 45nm requires devices that deviate from the planar bulk

In modern CMOS technologies reliability issues limit the maximum operating voltage of transistors. This prevents the integration of efficient power amplifiers (e.g., audio or RF) since stacked devices are needed to preve

Kenji Hinode1, Hideo Suzuki1, Toshiyuki Miyazaki2, Mutsuo Hidaka1, Nobuyuki Yoshikawa3, Hirotaka Terai4, Akira Fujimaki5 International Superconductivity Technology Center, Tsukuba, Japan Japan Science and Technology Agen

Jun Noda2, Teruki Sukenari2, Yusuke Konishi2, Toshiyasu Nakao2, Akitake Mitsuhashi2, Daigo Taguchi1 1 NEC, Kawasaki, Japan, 2NEC, Ikoma, Japan Wireless sensor network systems are coming into increased use because of thei

performance attainable in already available technologies. Above-IC technology (A-IC), consisting of a 5μm thick electroplated Cu layer on an 18μm low-K BCB dielectric, post-processed on top of the CMOS, provides a low-co

Although software-defined radio (SDR) transceivers that operate with many current and future wireless systems (i.e., cellular, WLAN, WPAN, broadcast and GPS standards) have been extensively developed [1-2], demands for e