ISSCC 2009
Session 6
RF & Wireless
An Integrated Closed-Loop Polar Transmitter with Saturation Prevention and Low-IF Receiver for QuadBand GPRS/EDGE is then prevented by backing off the requested transmit power. Another signal from the PA, should it enter the saturation region, alters the slew rate of the recovery.
Thomas Obkircher1, Mohamed El Said1, Bala Ramachandran2, Tirdad Sowlati1, Darioush Agahi1, WeiHong Chen1, Dean A. Badillo1, Masoud Kahrizi1, Jaleh Komaili1, Stephane Wloczysiak1, Utku Seckin1, Yun-Young Choi1, Hasan Akyo
ISSCC 2009
Session 6
RF & Wireless
A SAW-Less Multiband WEDGE Receiver
Fabio T. Braz1, Richard Gudmundsson2, Thomas Mattsson2, Carine Lascaux1, Christophe Trichereau1, Wen Suter3, Eric Westesson2, Andreas Nydahl2 ST-NXP Wireless, Caen, France, 2Ericsson Mobile Platforms, Lund, Sweden Ericss
ISSCC 2009
Session 6
RF & Wireless
Single-Chip Multiband WCDMA/HSDPA/HSUPA/EGPRS Transceiver with Diversity Receiver and 3G DigRF Interface Without SAW Filters in Transmitter / 3G Receiver Paths
Mohamed El Said, John Vasa, Bala Ramachandran, Masoud Kahrizi, Elias Dagher, Wei-Hong Chen, Martin Vadkerti, Georgi Taskov, Utku Seckin, Hamid Firouzkouhi, Behzad Saeidi, Hasan Akyol, Yunyoung Choi, Amir Mahjoob, Sandeep
ISSCC 2009
Session 6
RF & Wireless
Single-Chip RF CMOS UMTS/EGSM Transceiver with Integrated Receive Diversity and GPS
B. Ahrari2, R. Brockenbrough2, J. Chen2, C. Donovan2, R. Jonnalagedda2, J. Kim2, J. Ko2 , H. Lee2 , S. Lee2, E. Lei2, T. Nguyen2, T.Pan2, S. Sridhara1, W. Su1, H. Yan1, J. Yang2, C. Conroy2, C. Persico1, K. Sahota1, B. K
ISSCC 2009
Session 6
RF & Wireless
A 45nm Low-Power SAW-less WCDMA Transmit Modulator Using Direct Quadrature Voltage Modulation
In FDD systems such as WCDMA and LTE, TX and RX operate simultaneously, while the duplexer provides the necessary isolation between them. In order not to desensitize the RX path, the TX noise in WCDMA band 1 has to be lo
ISSCC 2009
Session 6
RF & Wireless
An Embedded 65nm CMOS Low-IF 48MHz-to-1GHz Dual Tuner for DOCSIS 3.0
L. Dauphinee, J. Xiao, D.S.-H. Chang, T.-H. Chih, M. Brandolini, D. Koh, B. J.-J. Hung, T. Wu, M. Introini, G. Cusmai, L. Tan, B. Currivan, L. He, P. Cangiane, P. Vorenkamp Broadcom, Irvine, CA The increased competition
ISSCC 2009
Session 6
RF & Wireless
A 1.2V 67mW 4mm2 Mobile ISDB-T Tuner in 0.13µm CMOS
The widespread use of mobile TV applications has been anticipated in the past few years. In Japan ISDB-T mobile TV service was started in 2006 and within less than 2 years, mobile phones with TV function have become main
ISSCC 2009
Session 7
Memory
V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with Hybrid-I/O Sense Amplifier and Segmented SubArray Architecture
Seok-Hun Hyun, Byung-Chul Kim, In-Chul Jeong, Seong-Young Seo, Jun-Ho Shin, Seok-Woo Choi, Ho-Sung Song, Jung-Hwan Choi, Kye-Hyun Kyung, Young-Hyun Jun, Kinam Kim Samsung Electronics, Hwasung, Korea As the workload and s
ISSCC 2009
Session 7
Memory
8Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology
Hoon Lee, Soo-Ho Cha, Jaesung Ahn, DukMin Kwon, Jin Ho Kim, Jae-Wook Lee, Han-Sung Joo, Woo-Seop Kim, Hyun-Kyung Kim, Eun-Mi Lee, So-Ra Kim, Keum-Hee Ma, Dong-Hyun Jang, Nam-Seog Kim, Man-Sik Choi, Sae-Jang Oh, Jung-Bae
ISSCC 2009
Session 7
Memory
A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with Controllable Repeater and On-the-Fly Power-Cut Scheme for Low-Power and High-Speed Mobile Application
Lee, Duck Hwa Hong, Jae Hoon Kim, Eun Ryeong Lee, Min Chang Kim, Kyung Ha Lee, Sang Il Park, Jong Ho Son, Sang Kwon Lee, Seong Nyuh Yoo, Sung Mook Kim, Tae Woo Kwon, Jin Hong Ahn, Yong Tak Kim Hynix Semiconductor, Icheon
ISSCC 2009
Session 7
Memory
75nm 7Gb/s/pin 1Gb GDDR5 Graphics Memory Device with Bandwidth-Improvement Techniques
S. Kieser, D. Kehrer, M. Kuzmenka, U. Moeller, P. Petkov, M. Plan, M. Richter, I. Russell, K. Schiller, R. Schneider, K. Swaminathan, B. Weber, J. Weber, I. Bormann, F. Funfrock, M. Gjukic, W. Spirkl, H. Steffens, J. Wel
ISSCC 2009
Session 7
Memory
Single-Ended Transceiver Design Techniques for 5.33Gb/s Graphics Applications
Russell Homer1, Otto Schumacher2, Reinhold Unterricker2, Werner Kederer2 Qimonda, San Jose, CA Qimonda, Munich, Germany 1 2 Graphics processing is the driving force behind the demand for high-bandwidth DRAMs. Acceleratin
ISSCC 2009
Session 7
Memory
A 6Gb/s/pin Pseudo-Differential Signaling Using Common-Mode Noise Rejection Techniques Without Reference Signal for DRAM Interfaces
parallel links as well as in high-speed serial links. However, differential signaling is not cost effective for DRAM interfaces because the I/O-pin count is a significant portion of the chip cost. Since differential sign
ISSCC 2009
Session 7
Memory
A 1.6V 3.3Gb/s GDDR3 DRAM with Dual-Mode Phase- and Delay-Locked Loop Using Power-Noise Management with Unregulated Power Supply in 54nm CMOS
Jong-Jin Lee, Ki-Han Kim, Shin-Deok Kang, Ji-Yeon Yang, Jae-Suck Kang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee,
ISSCC 2009
Session 7
Memory
Low-Vt Small-Offset Gated Preamplifier for Sub-1V Gigabit DRAM Arrays
achieves fast sensing, fast local I/O driving and low-leakage operation simultaneously even for low-voltage mid-point sensing. The features are verified with a 70nm 128Mb DRAM core that demonstrates 16.4ns row access (tR
ISSCC 2009
Session 8
Digital Processors
An Ultra-Low-Energy/Frame Multi-Standard JPEG CoProcessor in 65nm CMOS with Sub/Near-Threshold Power Supply
NXP Semiconductors, Eindhoven, Netherlands 3 National University of Singapore, Singapore power switch transistors S0, S1 and S2 are designed with NMOS transistors with their gate control voltage boosted to 1.2V, which is
ISSCC 2009
Session 8
Digital Processors
A Versatile Recognition Processor Employing HaarLike Feature and Cascaded Classifier
This paper presents a versatile recognition processor that performs detection and recognition of image, video, sound and acceleration signals, while dissipating 0.15µW/fps to 0.47mW/fps (Fig. 8.2.1). Given the low power
ISSCC 2009
Session 8
Digital Processors
A 201.4GOPS 496mW Real-Time Multi-Object Recognition Processor with Bio-Inspired Neural Perception Engine
recognition [1], was applied to the implementation of a high performance object recognition chip [2]. Even though the previous chip achieved 50% gain of computational cost [2], it could recognize only one object in a fra
ISSCC 2009
Session 8
Digital Processors
A Multi-Format Blu-ray Player SoC in 90nm CMOS
Lan, Chien-Hua Wu, Ting-Hsun Wei, Chi-Chin Lien, Jiun-Yuan Wu, Chih-Hao Hsiao, Te-Wei Chen, Yeh-Lin Chu, Guan-Yi Lin, Yung-Chang Chang, Kung-Sheng Lin, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Chien-H
ISSCC 2009
Session 8
Digital Processors
A 212MPixels/s 4096×2160p Multiview Video Encoder Chip for 3D/Quad HDTV Applications
Chiu, Yu-Han Chen, Pai-Heng Hsiao, Shao-Yi Chien, Tung-Chien Chen, Ping-Chih Lin, Chia-Yu Chang, Liang-Gee Chen National Taiwan University, Taipei, Taiwan To provide more vivid perception, TV resolution is increasing dra
ISSCC 2009
Session 8
Digital Processors
A 45nm Single-Chip Application-and-Baseband Processor Using an Intermittent Operation Technique
Hiroo Yamamoto, Sachio Ogawa, Takuya Arimura, Hiroshi Hirai, Yasuo Iizuka, Tsutomu Sekibe, Yoichi Nishida, Toshiyuki Ishioka, Junji Michiyama Panasonic, Yokohama, Japan Mobile phones demand high-performance application p
ISSCC 2009
Session 8
Digital Processors
A 342mW Mobile Application Processor with Full-HD Multi-Standard Video Codec
Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori Renesas Technology, Tokyo, Japan Today’s cellular phones must
ISSCC 2009
Session 9
Data Converters
A 130mW 100MS/s Pipelined ADC with 69dB SNDR Enabled by Digital Harmonic Distortion Correction
A pipelined ADC is presented with 2 fully integrated digital background calibration techniques: harmonic distortion correction (HDC) to compensate for residue amplifier gain error and nonlinearity, and DAC noise cancella
ISSCC 2009
Session 9
Data Converters
A 50MS/s 9.9mW Pipelined ADC with 58dB SNDR in 0.18µm CMOS Using Capacitive Charge-Pumps
pipelined ADCs, several power-efficient pipelined ADCs have recently been proposed. The most promising topologies reported thus far are those that substitute the opamp, which is the largest consumer of power in pipelined
ISSCC 2009
Session 9
Data Converters
A 12b 50MS/s Fully Differential Zero-Crossing-Based ADC Without CMFB
As intrinsic device gain and power supply voltages decrease with CMOS technology scaling, it is becoming increasingly challenging for designers of conventional opamp-based switched-capacitor circuits to meet gain and out
ISSCC 2009
Session 9
Data Converters
A 9b 14µW 0.06mm2 PPM ADC in 90nm Digital CMOS
University of Michigan, Ann Arbor, MI, National Semiconductor, Salem, NH As CMOS dimensions scale down, time-domain resolution of digital signals improves but the voltage resolution of analog signals degrades [1]. In thi
ISSCC 2009
Session 9
Data Converters
A 0.13µm CMOS 78dB SNDR 87mW 20MHz BW CT ∆Σ ADC with VCO-Based Integrator and Quantizer
based ADCs have become a topic of great interest due to the unique and attractive signal-processing properties they offer in the design of oversampling converters. Assuming a ring-oscillator structure, the outputs of a V
ISSCC 2009
Session 9
Data Converters
A 1.2V 2MHz BW 0.084mm2 CT ∆Σ ADC with -97.7dBc THD and 80dB DR Using Low-latency DEM
Due to their inherent anti-aliasing properties and potential for low-power design, continuous-time (CT) ∆Σ ADCs are an indispensable component in wireless communication systems such as GSM/WCDMA, since a precise sampling
ISSCC 2009
Session 9
Data Converters
A 20MHz BW 68dB DR CT ∆Σ ADC Based on a MultiBit Time-Domain Quantizer and Feedback Element
Edgar Sánchez-Sinencio1, Jose Silva-Martinez1, Chinmaya Mishra1,2, Lei Chen1, Erik Pankratz1 1 Texas A&M University, College Station, TX Qualcomm, San Diego, CA 2 Low-power, small-area, 20MHz-BW ADCs that can be integrat
ISSCC 2009
Session 9
Data Converters
A Multirate 3.4-to-6.8mW 85-to-66dB DR GSM/Bluetooth/UMTS Cascade DT ∆ΣΜ in 90nm Digital CMOS can be adjusted according to the required sampling frequency by changing the output stage bias. The 1.5b quantizer consists of 2 comparators and a switched-capacitor network that generates a voltage shift of
Yves Rolain2, Geert Van der Plas1 for the comparator input signals. The comparator is based on a dynamic regenerative latch driving an SR latch. The reference voltage of the DAC is 0.8V. 9.8 IMEC, Leuven, Belgium Vrije U
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