ISSCC 2009
Session 26
Other
Multiple-Output Step-Up/Down Switching DC-DC Converter with Vestigial Current Control
Kyoung-Sik Seol1,4, Young-Jin Woo1, Gyu-Hyeong Cho1, Gyu-Ha Cho2, Jae-Woo Lee2, Sung-il Kim3 Control-loop compensation: There are two poles in the conventional CPM control loop (one is generated by the error amplifier, a
ISSCC 2009
Session 26
Other
Single-Inductor Dual-Input Dual-Output Buck-Boost Fuel-Cell-Li-Ion Charging DC-DC Converter Supply
Self-powered wireless micro-sensors and other miniaturized wireless systems provide energy-saving and performance-enhancing intelligence to state-ofthe-art biomedical and consumer electronics and difficult-to-replace tec
ISSCC 2009
Session 26
Other
Digitally Assisted Quasi-V2 Hysteretic Buck Converter with Fixed Frequency and without Using Large-ESR Capacitor
The rapid advancement of processor technology has posed stringent challenges on power supply design. For high efficiency, switching converters are used. Frequent load switching requires the converters to have fast load t
ISSCC 2009
Session 26
Other
A 20W/channel Class-D Amplifier with Significantly Reduced Common-Mode Radiated Emissions
Due to their rail-to-rail switching nature, Class-D audio amplifiers are prone to generating electromagnetic interference (EMI) that is in excess of what is acceptable in many systems. Such systems typically require devi
ISSCC 2009
Session 26
Other
Two Class-D Audio Amplifiers with 89/90% Efficiency and 0.02/0.03% THD+N Consuming Less than 1mW of Quiescent Power
The high efficiency of Class-D amplifiers (CDAs) makes them highly attractive candidates for audio drivers in systems with extremely low-power requirements. However, to achieve low distortion, the audio modulator is usua
ISSCC 2009
Session 26
Other
A 460W Class-D Output Stage with Adaptive Gate Drive Marco Berkhout
many consumer applications such as television and home-theatre systems. The high efficiency of Class-D amplifiers allows for providing a very high output power with a modest heat sinking. The audio amplifier market has a
ISSCC 2009
Session 27
Memory
A 4.0 GHz 291Mb Voltage-Scalable SRAM Design in 32nm High-κ Metal-Gate CMOS with Integrated Power Management
Y. Zhang, K. Zhang, M. Bohr Intel, Hillsboro, OR CMOS technology has followed Moore’s law into the nanoscale regime where SRAM scaling is facing increasing challenges in gaining performance at reduced leakage power for f
ISSCC 2009
Session 27
Memory
A Process–Variation-Tolerant Dual-Power-Supply SRAM with 0.179µm2 Cell in 40nm CMOS Using Level-Programmable Wordline Driver
T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, T. Nakazato, Y. Shizuki, N. Kushiyama, T. Yabe Toshiba Semiconductor, Kawasaki, Japan A 512Kb dual-power-supply SRAM is fabricated in 40nm CMOS with 0.179µm2 cell, which is
ISSCC 2009
Session 27
Memory
A 2ns-Read-Latency 4Mb Embedded Floating-Body Memory Macro in 45nm SOI Technology
Philippe Bauser1, Paul de Champs1, Hamid Daghighian1, David Fisch1, Philippe Graber1, Michel Bron1 Innovative Silicon, Lausanne, Switzerland, 2AMD, Fort Collins, CO 1 To meet advancing market demands, microprocessor embe
ISSCC 2009
Session 27
Memory
A 90nm 12ns 32Mb 2T1MTJ MRAM
Y. Kato1, K. Mori1, Y. Ozaki2, Y. Kobayashi2, N. Ohshima1, K. Kinoshita1, T. Suzuki1, K. Nagahara1, N. Ishiwata1, K. Suemitsu1, S. Fukami1, H. Hada1, T. Sugibayashi1, N. Kasai1 NEC, Sagamihara, Japan, 2NEC Electronics, S
ISSCC 2009
Session 27
Memory
A 1.6GB/s DDR2 128Mb Chain FeRAM with Scalable Octal Bitline and Sensing Schemes
Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko Doumae, Shoichi Shimizu, Mitsumo Kawano
ISSCC 2009
Session 28
Other
Optical I/O Technology for Tera-Scale Computing
to many-core will drive increased chip-to-chip I/O bandwidth demands at processor/memory interfaces and in multi-processor systems. Future architectures will require bandwidths of 200GB/s to 1.0TB/s and will bring about
ISSCC 2009
Session 28
Other
Wireless DC Voltage Transmission Using InductiveCoupling Channelfor Highly-Parallel Wafer-Level Testing
increased each year; the test cost especially for low-price IC chips, for example, exceeds one-third of total chip cost. Furthermore, screening test on wafer to select good dies (KnownGood-Die) will become more significa
ISSCC 2009
Session 28
Other
A Stretchable EMI Measurement Sheet with 8×8 Coil
Koichi Ishida1, Naoki Masunaga1, Zhiwei Zhou1, Tadashi Yasufuku1, Tsuyoshi Sekitani1, Ute Zschieschang2, Hagen Klauk2, Makoto Takamiya1, Takao Someya1, Takayasu Sakurai1 1 University of Tokyo, Tokyo, Japan Max Planck Ins
ISSCC 2009
Session 28
Other
Field-Coupled Nanomagnets for Interconnect-Free Nonvolatile Computing
field-coupled single-domain magnets is promising for rad-hard, nonvolatile, dense and highly parallel digital information processing. The shortcomings of metal wiring are overcome as no current flow is needed for the log
ISSCC 2009
Session 28
Other
Chip Scale Camera Module (CSCM) Using ThroughSilicon-Via (TSV)
Nishimura, Kazumasa Tanida, Kazutaka Akiyama, Masahiro Sekiguchi, Mie Matsuo, Satoru Fukuchi, Katsutomu Takahashi Toshiba Semiconductor, Yokohama, Japan No one doubts that Through Silicon Via (TSV) is one of the necessar
ISSCC 2009
Session 28
Other
A Subjective-Contour Generation LSI System with Expandable Pixel-Parallel Architecture for Vision Systems
Media processors that can be applied to vehicle or robot vision have been developed previously [1]. However, even using the latest media processors, the ability of artificial vision is far below that of human vision. All
ISSCC 2009
Session 28
Other
An Inductive-Coupling Link for 3D Integration of a 90nm CMOS Processor and a 65nm CMOS SRAM
Yoshinori Kohama1, Kazutaka Kasuga1, Itaru Nonomura2, Makoto Saen3, Shigenobu Komatsu3, Kenichi Osada3, Naohiko Irie3, Toshihiro Hattori2, Atsushi Hasegawa2, Tadahiro Kuroda1 1 Keio University, Yohohama, Japan 2 Renesas
ISSCC 2009
Session 29
mm-Wave
A 1.1V 150GHz Amplifier with 8dB Gain and +6dBm Saturated Output Power in Standard Digital 65nm CMOS Using Dummy-Prefilled Microstrip Lines
Luis Chen1, C. Patrick Yue1, Mark Rodwell1 University of California, Santa Barbara, CA IBM, Burlington, VT 3 IBM, Crolles, France 1 2 Radio applications beyond 100GHz that will benefit from silicon technologies [1-5] inc
ISSCC 2009
Session 29
mm-Wave
W-Band CMOS Amplifiers Achieving +10dBm Saturated Output Power and 7.5dB NF
The scaling of CMOS technology has led to development of amplifiers up to 100GHz and even beyond. As the technology enables the integration of many functions on silicon and is suitable for mass production, the cost-effec
ISSCC 2009
Session 29
mm-Wave
A 26dB-Gain 100GHz Constructive-Wave Amplifier Si/SiGe Cascaded
The availability of W-band (75 to 111GHz) silicon integrated circuits will potentially revolutionize medical and security imaging, as well as high-capacity wireless communications. Traditional W-band circuits rely on GaA
ISSCC 2009
Session 29
mm-Wave
A Dual-Mode Architecture for a Phased-Array Receiver Based on Injection Locking in 0.13µm CMOS
Phased arrays have long been used by the military for radar applications, but have only been recently applied to consumer applications. In a phased array system, one or more narrow beams are generated by transmitting (or
ISSCC 2009
Session 29
mm-Wave
A Digitally Controlled Compact 57-to-66GHz Front-End in 45nm Digital CMOS
high-datarate communication [1-4]. From a cost perspective, a highly integrated solution is favorable. Speed and power consumption considerations for the highdata-rate digital part of the chip make 45nm CMOS a very reali
ISSCC 2009
Session 29
mm-Wave
A 57-to-66GHz Quadrature PLL in 45nm Digital CMOS
for high-data-rate communication. Despite the large amount of research on CMOS mm-wave frequency generation, current state-of-the-art mm-wave PLLs [1-5] do not achieve a tuning range that is wide enough to cover the worl
ISSCC 2009
Session 29
mm-Wave
A 59GHz Push-Push VCO with 13.9GHz Tuning Range Using Loop-Ground Transmission Line for a FullBand 60GHz Transceiver
60GHz wireless communication systems, using the unlicensed frequency band from 57 to 66GHz, are expected to make high-data-rate transfer possible. IEEE 802.15.3c is finalizing a radio-frequency (RF) allocation composed o
ISSCC 2009
Session 3
Digital Processors
A 45nm 8-Core Enterprise Xeon® Processor
of eight dualthreaded 64b Nehalem cores and a shared L3 cache. The system interface includes two on-chip memory controllers and supports multiple system topologies. Figure 3.1.1 shows the processor block diagram. This de
ISSCC 2009
Session 3
Digital Processors
A Family of 45nm IA Processors
Nehalem is a family of next-generation IA processors for mobile, desktop and server segments implemented in 45nm high-κ metal-gate CMOS [1]. The family features a new system architecture, significantly enhanced Core arch
ISSCC 2009
Session 3
Digital Processors
A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors
number of dedicated functional IP cores, including 3D graphics and video codec, and require local memories with high bit density. Each IP core is connected to closely positioned local memories for fast access and wide ba
ISSCC 2009
Session 3
Digital Processors
Dynamic Frequency-Switching Clock System on A Quad-Core Itanium® Processor
Intel, Fort Collins, CO The 700mm2 65nm Itanium® processor codenamed Tukwila [1] integrates four cores and a system interface with six QuickPath® interconnect channels and four memory interconnect channels. The large die
ISSCC 2009
Session 3
Digital Processors
Secure AES Engine with A Local Switched-Capacitor Current Equalizer
Hardware implementations of the popular AES encryption algorithm [1,2] provide attackers with important side-channel information (delay, power consumption or EM radiation) that can be used to disclose the secret key of t
ISSCC 2009
Session 3
Digital Processors
A 4Gb/s/ch 356fJ/b 10mm Equalized On-chip Interconnect with Nonlinear Charge-Injecting Transmit Filter and Transimpedance Receiver in 90nm CMOS
This paper presents a transceiver for fast and energy-efficient global on-chip communication, consisting of a nonlinear charge-injecting (CI) 3-tap transmit filter (TX) and a sampling receiver (RX) with transimpedance pr
ISSCC 2009
Session 3
Digital Processors
Dual-DLL-Based CMOS All-Digital Temperature Sensor for Microprocessor Thermal Monitoring
increasingly need on-chip temperature sensors for thermal and power management [1]. Since these sensors do not take part in the main computing activity but rather play the auxiliary, albeit important, role of temperature
ISSCC 2009
Session 3
Digital Processors
Over One Million TPCC with a 45nm 6-Core Xeon® CPU This paper describes the 6-core Xeon® 7400 series processor family, codename Dunnington, designed for a broad range of highly power efficient servers. The processor consists of three dual-core 45nm CoreTM processors [1] and a shared inclusive 16MB L3 cache (LLC) integrated on a monolithic 503mm2 die. The system interface is FSB based with the I/Os incorporated into the center of the die. Figure 3.8.1 shows the chip floorplan. The core-to-FSB connection is replaced with an on-die low-latency uncore interface. The uncore arbitrates among core, LLC, and external bus requests. The processor has 1.9B transistors and is implemented in 45nm CMOS using high-κ metalgate transistors and nine copper interconnect layers [2]. The maximum thermal design power is 130W. There are 8 PLLs on a single die with a cascaded pair serving its respective
high-frequency clock (GCLK) supporting the core; and a half- frequency clock that supports most of the uncore logic and the LLC. In the cascaded configuration, the I/O PLL receives the xxCLK and synthesizes the 4× freque
ISSCC 2009
Session 4
Data Converters
A 12b 2.9GS/s DAC with IM3 <-60dBc Beyond 1GHz in 65nm CMOS
E. Ayranci2, X. Liu2, K. Bult2 Broadcom, Irvine, CA Broadcom, Bunnik, Netherlands 1 2 A 12b 2.9GS/s current-steering DAC implemented in 65nm CMOS is presented, with an IM3 <-60dBc beyond 1GHz while driving a 50Ω load wit
ISSCC 2009
Session 4
Data Converters
A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP Digital CMOS
high-speed communication systems, such as serial links, UWB, and OFDM-based 60GHz receivers. Due to complex DSP and low-power constraints, digital basebands are designed in low-leakage, high-VT low-power (LP) CMOS proces
ISSCC 2009
Session 4
Data Converters
A 1.8V 1.0GS/s 10b Self-Calibrating Unified-FoldingInterpolating ADC with 9.1 ENOB at Nyquist Frequency
T. Hoehn1, P. Schmitz1, H. Werker1, A. Glenny3 National Semiconductor, Unterhaching, Germany National Semiconductor, Greenock, United Kingdom 3 National Semiconductor, Santa Clara, CA 1 2 correct stage N-1’s decision, re
ISSCC 2009
Session 4
Data Converters
A 5b 800MS/s 2mW Asynchronous Binary-Search ADC in 65nm CMOS
low-power high-speed ADCs to convert RF/IF signals into digital form for subsequent baseband processing. Considering latency and conversion speed, flash ADCs are often the most preferred option. Generally, flash ADCs suf
ISSCC 2009
Session 4
Data Converters
A 600MS/s 30mW 0.13µm CMOS ADC Array Achieving Over 60dB SFDR with Adaptive Digital Equalization
Industrial Technology Research Institute, Hsinchu, Taiwan Since the front-end T/H stage and the two buffers are out of the calibration loop, it is crucial for them to maintain better-than-8b linearity at 600MS/s. A pseud
ISSCC 2009
Session 4
Data Converters
A 10b 500MHz 55mW CMOS ADC
Recent work on ADCs targeting sampling rates of hundreds of MHz with resolutions in the range of 10 to 11b has faced speed limitations with a single channel [1] or employed interleaving, but with a relatively high power
ISSCC 2009
Session 4
Data Converters
A 16b 125MS/s 385mW 78.7dB SNR CMOS Pipeline ADC
ADCs with emphasis on low power, and the ability to IF-sample to reduce receiver complexity. Further, the often-overlooked metric of small-signal linearity, quantified by SFDR for less-than-full-scale inputs is important
ISSCC 2009
Session 5
Wireline I/O
A 7.1mW 10GHz All-Digital Frequency Synthesizer with Dynamically Reconfigurable Digital Loop Filter in 90nm CMOS
ADPLL frequency synthesizers have recently drawnsignificant research attention as the technology paradigm shifts into the nanometer CMOS arena [1-5]. They circumvent several design issues that conventional charge-pump-ba
ISSCC 2009
Session 5
Wireline I/O
A VDSL2 CPE AFE in 0.15µm CMOS with Integrated Line Driver
VDSL2 transceivers use a wide analog bandwidth to achieve bit-rates in excess of 200Mb/s. For standard 6-band VDSL2, 30MHz bandwidth is required, comprising three up-stream and three down-stream signals. Since discrete m
ISSCC 2009
Session 5
Wireline I/O
Subharmonically Injection-Locked PLLs for UltraLow-Noise Clock Generation
In this paper, complete analysis and validation of subharmonic injection locking that can substantially reduce the PLL phase noise at negligible cost is presented. Two 20GHz PLLs based on this technique demonstrate 149 a
ISSCC 2009
Session 5
Wireline I/O
Bang-Bang Digital PLLs at 11 and 20GHz with sub200fs Integrated Jitter for High-Speed Serial Communication Applications
Z. Toprak Deniz, D. Friedman IBM T.J. Watson Research Center, Yorktown Heights, NY Wireline communication applications typically require a low-phase-noise wide-tuning-range PLL. While these requirements can be met using
ISSCC 2009
Session 5
Wireline I/O
mW 7GHz and 1.6mW 60GHz Frequency Dividers with Locking-Range Enhancement in 0.13µm CMOS
Frequency dividers are key components for frequency synthesis in wireless and wireline communication systems. Among different types of frequency dividers, LC-based injection-locked frequency dividers (ILFDs) feature high
ISSCC 2009
Session 5
Wireline I/O
A 5.4mW 0.0035mm2 0.48psrms-Jitter 0.8-to-5GHz Non-PLL/DLL All-Digital Phase Generator/Rotator in 45nm SOI CMOS
Seongwon Kim1, Sergey V. Rylov1, Daniel J. Friedman1 1 IBM T.J. Watson, Yorktown Heights, NY IBM, Austin, TX 3 IBM, Poughkeepsie, NY and nine 4× legs, yielding a total of 40 realizable steps within a quadrant and 160 ste
ISSCC 2009
Session 5
Wireline I/O
A 14mW 5Gb/s CMOS TIA with Gain-Reuse Regulated Cascode Compensation for Parallel Optical Interconnects
Hugh J. Barnaby, Bert Vermeire, Sayfe Kiaei Arizona State University, Tempe, AZ Short-distance parallel optical links are poised to replace copper interconnects in high throughput links between computing nodes. In the re
ISSCC 2009
Session 5
Wireline I/O
A 4Gb/s Current-Mode Optical Transceiver in 0.18µm CMOS
a number of high-speed digital interface standards have been introduced: LVDS, HDMI, DVI, etc [1]. DisplayPort is a digital display interface standard that is recently introduced in an attempt to meet future demands on t
ISSCC 2009
Session 5
Wireline I/O
Jitter-Reduction and Pulse-Width-Distortion Compensation Circuits for a 10Gb/s Burst-Mode CDR Circuit
burst-mode CDR circuit must be able to retime and reshape the input data. In this paper, a burst-mode CDR circuit is presented that achieves output-datajitter reduction of 3dB at jitter frequency of 1GHz, synchronization
ISSCC 2009
Session 5
Wireline I/O
CMOS Optical 4-PAM VCSEL Driver with ModalDispersion Equalizer for 10Gb/s 500m MMF Transmission
Data communication over 300m of distance, such as Ethernet standards, where the required data rate per channel reaches 10Gb/s or more, demand optical transmission [1]. Vertical-cavity surface-emitting laser (VCSEL) and m