ISSCC 2010

2010

210 篇论文 · RF & Wireless (33) · Memory (24) · mm-Wave (18) · Digital Circuits (18) · Digital Processors (16)

ISSCC 2010 Session 9 Digital Circuits
Within-Die Variation-Aware Dynamic-VoltageFrequency Scaling Core Mapping and Thread Hopping for an 80-Core Processor
Saurabh Dighe1, Sriram Vangal1, Paolo Aseron1, Shasi Kumar2,
Tiju Jacob2, Keith Bowman1, Jason Howard1, James Tschanz1, Vasantha Erraguntla2, Nitin Borkar1, Vivek De1, Shekhar Borkar1 1 Intel, Hillsboro, OR Intel, Bangalore, India 2 Many-core processors with on-die network-on-chip
ISSCC 2010 Session 9 Digital Circuits
A Precise-Tracking NBTI-Degradation Monitor Independent of NBTI Recovery Effect
Eisuke Saneyoshi, Koichi Nose, Masayuki Mizuno
Scaling has accelerated transistor degradation with respect to aging, especially for Negative Bias Temperature Instability (NBTI), which can cause more than a 10% degradation in delay [1]. It is known that in NBTI condit
NEC, Kanagawa, Japan
ISSCC 2010 Session 9 Digital Circuits
Low-Skew Clock Distribution Using Zero-PhaseClock-Buffer DLLs
Ting Wu, Farshid Aryanfar, Hae-Chang Lee, Jie Shen, TJ Chin,
Carl Werner, Ken Chang Rambus, Los Altos, CA Clock distribution continues to be a challenging task in digital clocked systems. In a typical clocking architecture (Fig. 9.2.1, top), a phase-locked loop (PLL) produces the
ISSCC 2010 Session 9 Digital Circuits
POWER7TM Local Clocking and Clocked Storage Elements
James Warnock1, Leon Sigal2, Dieter Wendel3, K Paul Muller4,
Joshua Friedrich5, Victor Zyuban2, Ethan Cannon6, A.J. KleinOsowski6 1 IBM Systems and Technology Group, Yorktown Heights, NY IBM Research, Yorktown Heights, NY 3 IBM Systems and Technology Group, Boeblingen, Germany 4 I
ISSCC 2010 Session 9 Digital Circuits
A 1.2 TB/s On-Chip Ring Interconnect for 45nm 8-Core Enterprise Xeon® Processor
Cheolmin Park, Roy Badeau, Larry Biro, Jonathan Chang,
Xeon microprocessors targeting high performance, low-power products [1, 2]. Several key design requirements for this product include high bandwidth, low-latency shared L3 cache access, design modularity to support effici
Tejpal Singh, Jim Vash, Bo Wang, Tom Wang Intel, Hudson, MA Nehalem-EX
ISSCC 2010 Session 9 Digital Circuits
High-Bandwidth and Low-Energy On-Chip Signaling with Adaptive Pre-Emphasis in 90nm CMOS
Jae-sun Seo1, Ron Ho2, Jon Lexau2, Michael Dayringer2,
wires pose well-known latency, bandwidth, and energy challenges to the designers of high-performance VLSI systems. Repeaters effectively mitigate wire RC effects but do little to improve their energy costs. Moreover, pro
Dennis Sylvester1, David Blaauw1 1 University of Michigan, Ann Arbor,
ISSCC 2010 Session 9 Digital Circuits
A Microcontroller-Based PVT Control System For A 65nm 72Mb Synchronous SRAM
Sherif T Eid, Morgan Whately, Sandeep Krishnegowda
Cypress Semiconductor, San Jose, CA As scaling of silicon CMOS technology continues more challenges emerge in dealing with process variations. In SRAMs process variations directly affect operating margin, subthreshold le
ISSCC 2010 Session 9 Digital Circuits
Accurate Characterization of Random Process Variations Using a Robust Low-Voltage HighSensitivity Sensor Featuring Replica-Bias Circuit
Mesut Meterelliyoz1, Ashish Goel2, Jaydeep P. Kulkarni1, Kaushik Roy2, 1
random threshold voltage (Vth) fluctuations is crucial in process optimization and yield learning, particularly for matching critical transistors such as SRAMs, sense amplifiers, differential amplifiers, etc. Traditional
Intel, Hillsboro, OR Purdue University, West Lafayette, IN 2 Accurate
ISSCC 2010 Session 9 Digital Circuits
In Situ Delay-Slack Monitor for High-Performance Processors Using An All-Digital Self-Calibrating 5ps Resolution Time-to-Digital Converter
David Fick, Nurrachman Liu, Zhiyoong Foo, Matthew Fojtik,
susceptible to process, voltage, and temperature (PVT) variation. The standard approach for addressing this issue is to increase timing margin at the expense of power and performance. One approach to reclaim these losses
Jae-sun Seo, Dennis Sylvester, David Blaauw University of Michigan, An
ISSCC 2010 Session 9 Digital Circuits
Early Detection of Oxide Breakdown Through In Situ Degradation Sensing
Prashant Singh, Zhiyoong Foo, Michael Wieckowski, Scott Hanson,
high-performance design as it determines the maximum supply voltage, degrading maximum performance and SRAM stability [1]. OBD is an inherently statistical process where some devices fail long before others. Hence, a pri
Matt Fojtik, David Blaauw, Dennis Sylvester University of Michigan, An