ISSCC 2010

2010

210 篇论文 · RF & Wireless (33) · Memory (24) · mm-Wave (18) · Digital Circuits (18) · Digital Processors (16)

ISSCC 2010 Session 3 RF & Wireless
A 45nm WCDMA Transmitter Using Direct Quadrature Voltage Modulator with High Oversampling Digital Front-End
Xin He, Jan van Sinderen, Robert Rutten
In FDD systems such as WCDMA and LTE, simultaneous TX and RX operation poses a stringent TX noise floor requirement at the RX band. To eliminate the SAW filter between the TX and the PA without desensitizing the RX in WC
ISSCC 2010 Session 3 RF & Wireless
A 900MHz Direct ΔΣ Receiver in 65nm CMOS
Kimmo Koli1, Jarkko Jussila1, Pete Sivonen1, Sami Kallioinen2, Aarno Pärssinen2
Nokia Research Center, currently with ST-Ericsson, Turku, Finland, Nokia Research Center, Otaniemi Lablet, Espoo, Finland 2 Wireless communications is moving towards higher data rates but also requiring dynamic scalabili
ISSCC 2010 Session 3 RF & Wireless
A 10MHz Signal Bandwidth Cartesian-Loop Transmitter Capable of Off-Chip PA Linearization
Hiroaki Ishihara, Masahiro Hosoya, Shoji Otaka, Osamu Watanabe
Recently, signals with high peak-to-average power ratio (PAPR) are being used for metropolitan area networks (MANs) and cellular systems, and therefore highly linear transmitters (Txs) are required. The linearity perform
ISSCC 2010 Session 3 RF & Wireless
A 23mW Fully Integrated GPS Receiver with Robust Interferer Rejection in 65nm CMOS
Hyunwon Moon, Sangyoub Lee, Seung-Chan Heo, Hwayeal Yu,
are rapidly increasing in importance in our life. In particular, smart-phones with embedded GPS receivers are still growing their share and soon they will be the main products in the handset market. Co-existence of a GPS
ISSCC 2010 Session 3 RF & Wireless
A Low-Power Low-Noise Direct-Conversion FrontEnd with Digitally Assisted IIP2 Background Self Calibration
Yiping Feng1, Gaku Takemura2, Shunji Kawaguchi2, Nobuyuki Itoh2, Peter Kinget1
Columbia University, New York, NY Toshiba, Kawasaki, Japan 2 Direct conversion receivers offer a high level of integration for multiband applications. For standards operating in full duplex, like WCDMA, a very high IIP2
ISSCC 2010 Session 4 Analog Circuits
A Thermal-Diffusivity-Based Frequency Reference in Standard CMOS with an Absolute Inaccuracy of ±0.1% from -55°C to 125°C
Mahdi Kashmiri, Michiel Pertijs, Kofi Makinwa
Most electronic systems require a frequency reference, and so, much research has been devoted to the realization of on-chip frequency references in standard CMOS. However, the accuracy of such references is limited by th
ISSCC 2010 Session 4 Analog Circuits
A 34dB SNDR Instantaneously-Companding Baseband SC Filter for 802.11a/g WLAN Receivers
Vaibhav Maheshwari1, Wouter A. Serdijn1, John R. Long1, John J. Pekarik2
Delft University of Technology, Delft, Netherlands IBM, Burlington, VT 2 In wireless receivers, large dynamic range (DR) input signals necessitate additional power consumption in baseband active filters. A 5th order Cheb
ISSCC 2010 Session 4 Analog Circuits
A Micropower Chopper-Correlated Double-Sampling Amplifier with 2µV Standard Deviation Offset and 37nV/√Hz Input Noise Density
Massimiliano Belloni1, Edoardo Bonizzoni1, Andrea Fornasari2, Franco Maloberti1
University of Pavia, Pavia, Italy National Semiconductor, Rozzano, Italy 2 A key limit of the chopper stabilized technique is that the low-frequency noise after being shifted up to the chopping frequency is only partiall
ISSCC 2010 Session 4 Analog Circuits
A Single-Trim CMOS Bandgap Reference with a 3σ Inaccuracy of ±0.15% from -40°C to 125°C
Guang Ge1, Cheng Zhang1, Gian Hoogzaad1, Kofi Makinwa2, 1
15% (3σ) from -40ºC to 125ºC. This level of performance, previously only achieved by trimming at two or more temperatures [1, 2], was obtained by using chopping and curvature correction to minimize non-PTAT (proportional
ISSCC 2010 Session 4 Analog Circuits
A 21nV/√Hz Chopper-Stabilized Multipath CurrentFeedback Instrumentation Amplifier with 2µV Offset
Qinwen Fan, Johan H. Huijsing, Kofi A.A. Makinwa
Amplifiers with low offset and low 1/f noise usually employ auto-zeroing (AZ) and/or chopping. However, AZ suffers from noise aliasing, and so requires more power dissipation for a given noise specification. Chopping, al
ISSCC 2010 Session 4 Analog Circuits
A 10mW Stereo Audio CODEC in 0.13µm CMOS
Xicheng Jiang1, Jungwoo Song1, Todd L. Brooks1, Jianlong Chen1, Vinay
stereo audio CODECs are increasingly needed in wireless devices, such as Bluetooth headsets and smart phones. These portable devices are usually powered by low-voltage batteries with limited capacities. It is of particul
ISSCC 2010 Session 4 Analog Circuits
Class-G Headphone Driver in 65nm CMOS Technology
Alex Lollio1, Giacomino Bollati2, Rinaldo Castello1, 1
and DMB reception. The users may wish to use these features for many hours and a low efficiency amplifier could deplete the battery in a short time. There are two classes of power amplifiers usually used for this applica
ISSCC 2010 Session 4 Analog Circuits
45nm CMOS 8Ω Class-D Audio Driver with 79% Efficiency and 100dB SNR
Sreekiran Samala, Vineet Mishra, Kalyan Chekuri Chakravarthi
Integrating audio and power management into a system-on-chip (SoC) is of interest due to reduced board area and cost. Integrated Class-D audio drivers need to drive high voltages to deliver high power across small loads;
ISSCC 2010 Session 4 Analog Circuits
A 105dB-Gain 500MHz-Bandwidth 0.1Ω-OutputImpedance Amplifier for an Amplitude Modulator in 65nm CMOS
Chul Kim1,2, Chang-seok Chae1, Young-sub Yuk1, Yi-Gyeong Kim3,
modulation, where a constant-amplitude phase signal is amplified by an efficient switched-mode power amplifier (PA) and an envelope signal is modulated at the drain of the PA, has been proven to improve efficiency and li
ISSCC 2010 Session 4 Analog Circuits
A 3.2GHz-Sample-Rate 800MHz Bandwidth Highly Reconfigurable Analog FIR Filter in 45nm CMOS
Eoin O’hAnnaidh1,2, Emmanuel Rouat1, Sarah Verhaeren1,
hard disk drive and wireless video download, high-order filtering becomes increasingly difficult to realize in deep submicron CMOS technologies. Indeed CMOS transistors suffer from poor analog performances under reduced
ISSCC 2010 Session 5 Digital Processors
Westmere: A Family of 32nm IA Processors
Nasser A. Kurd, Subramani Bhamidipati, Christopher Mozak,
Jeffrey L. Miller, Timothy M. Wilson, Mahadev Nemani, Muntaquim Chowdhury Intel, Hillsboro, OR The Westmere processor is implemented on a high-κ metal-gate 32nm process technology [1] as a compaction of the Nehalem proce
ISSCC 2010 Session 5 Digital Processors
A 40nm 16-Core 128-Thread CMT SPARC SoC Processor
Jinuk Luke Shin, Kenway Tam, Dawei Huang, Bruce Petrick, Ha Pham,
Changku Hwang, Hongping Li, Alan Smith, Timothy Johnson, Francis Schumacher, David Greenhill, Ana Sonia Leon, Allan Strong Sun Microsystems, Santa Clara, CA This next generation of Chip Multithreaded (CMT) SPARC SoC proc
ISSCC 2010 Session 5 Digital Processors
A 45nm 37.3GOPS/W Heterogeneous Multi-Core SoC
Yoichi Yuyama1, Masayuki Ito1, Yoshikazu Kiyoshige1, Yusuke Nitta1,
Shigezumi Matsui1, Osamu Nishii1, Atsushi Hasegawa1, Makoto Ishikawa2, Tetsuya Yamada2, Junichi Miyakoshi2, Koichi Terada2, Tohru Nojiri2, Makoto Satoh2, Hiroyuki Mizuno2, Kunio Uchiyama2, Yasutaka Wada3, Keiji Kimura3,
ISSCC 2010 Session 5 Digital Processors
The Implementation of POWER7TM: A Highly Parallel and Scalable Multi-Core High-End Server Processor
Dieter Wendel1, Ronald Kalla2, Robert Cargoni2, Joachim Clables2,
Joshua Friedrich2, Roland Frech1, James Kahle2, Balaram Sinharoy3, William Starke2, Scott Taylor2, Steve Weitzel2, Sam G. Chu2, Saiful Islam2, Victor Zyuban4 1 IBM, Boeblingen, Germany IBM, Austin, TX 3 IBM, Poughkeepsie
ISSCC 2010 Session 5 Digital Processors
A Wire-Speed PowerTM Processor: 2.3GHz 45nm SOI with 16 Cores and 64 Threads
Charles Johnson1, David H. Allen2, Jeff Brown2, Steve Vanderwiel2,
Russ Hoover2, Heather Achilles3, Chen-Yong Cher4, George A. May5, Hubertus Franke4, Jimi Xenedis4, Claude Basso6 1 IBM Research, Rochester, MN IBM Systems and Technology Group, Rochester, MN 3 IBM Research, Bedford, NH 4
ISSCC 2010 Session 5 Digital Processors
An x86-64 Core Implemented in 32nm SOI CMOS
Ravi Jotwani1, Sriram Sundaram1, Stephen Kosonocky2, Alex Schaefer1,
occupies 9.69mm2, contains more than 35 million transistors (excluding L2 cache), and operates at frequencies in excess of 3GHz. The core incorporates numerous design and power improvements to enable an operating range o
ISSCC 2010 Session 5 Digital Processors
A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS
Jason Howard1, Saurabh Dighe1, Yatin Hoskote1, Sriram Vangal1,
David Finan1, Gregory Ruhl1, David Jenkins1, Howard Wilson1, Nitin Borkar1, Gerhard Schrom1, Fabrice Pailet1, Shailendra Jain2, Tiju Jacob2, Satish Yada2, Sraven Marella2, Praveen Salihundam2, Vasantha Erraguntla2, Micha
ISSCC 2010 Session 5 Digital Processors
A 4.1Tb/s Bisection-Bandwidth 560Gb/s/W Streaming Circuit-Switched 8×8 Mesh Network-on-Chip in 45nm CMOS
Mark A Anders, Himanshu Kaul, Steven K Hsu, Amit Agarwal,
core-to-core communication, are key to enabling future tera-scale multi-core processors. Packetswitched 2D mesh networks provide efficient interconnect utilization, low latencies and high throughputs, but suffer from low
ISSCC 2010 Session 6 Medical & Bio
A Mobile-Display-Driver IC Embedding a CapacitiveTouch-Screen Controller System
Hyoung-Rae Kim, Yoon-Kyung Choi, San-Ho Byun, Sang-Woo Kim,
Kwang-Ho Choi, Hae-Yong Ahn, Jong-Kang Park, Dong-Yul Lee, Zhong-Yuan Wu, Hyung-Dal Kwon, Yong-Yeob Choi, Chang-Ju Lee, Hwa-Hyun Cho, Jae-Suk Yu, Myunghee Lee Samsung Electronics, Yongin, Korea Touch-screen technologies,
ISSCC 2010 Session 6 Medical & Bio
A Double-Loop Control LED Backlight Driver IC for Medium-Sized LCDs
Seok-in Hong1, Jin-Wook Han1, Dong-Hee Kim2, Oh-Kyong Kwon1, 1
fluorescent lamp (CCFL) for LCD backlight units (BLU) for their lower power consumption, wider color gamut, and better dimming capability, in addition to being mercury-free [1, 2]. Recently, various studies have focused
ISSCC 2010 Session 6 Medical & Bio
Stable RGBW AMOLED Display with OLED Degradation Compensation Using Electrical Feedback
G. Reza Chaji1, Stefan Alexander1, J. Marcel Dionne1, Yaser Azizi1,
College London, London, United Kingdom Here, ΔVLUM is f(ΔVOLED(i,j)), and Vp(i,j), Vdata(i,j) and Vmonitor(i,j) are the gray scale value and two programming values for data and monitor lines for the pixel at ith row and
ISSCC 2010 Session 6 Medical & Bio
An Inductively Powered Scalable 32-Channel Wireless Neural Recording System-on-a-Chip for Neuroscience Applications
Seung Bae Lee, Hyung-Min Lee, Mehdi Kiani, Uei-Ming Jow, Maysam Ghovanloo
technology for interfacing with the central nervous system in laboratory animals and humans [1-2]. Even though these efforts have led to marvelous technological advancements in circuits and systems, some of the resulting
ISSCC 2010 Session 6 Medical & Bio
A 20µW Neural Recording Tag with Supply-CurrentModulated AFE in 0.13µm CMOS
Zhiming Xiao, Chun-Ming Tang, Christopher M. Dougherty, Rizwan Bashirullah
University of Florida, Gainesville, FL Perpetual measurement of brain activity in untethered small animal in-vivo experiments requires low power micro-systems incorporating amplification, A/D conversion, and short range
ISSCC 2010 Session 6 Medical & Bio
A 30µW Analog Signal Processor ASIC for Biomedical Signal Monitoring
Refet Firat Yazicioglu1, Sunyoung Kim1, Tom Torfs1, Patrick Merken2,
U. Leuven, Leuven, Belgium 2 Power efficiency of readout circuits for ambulatory monitoring of biopotential signals has been significantly improved during recent years [1]-[3], leaving digital signal processing (DSP) and
ISSCC 2010 Session 6 Medical & Bio
A 1V 22µW 32-Channel Implantable EEG Recording IC
Xiaodan Zou, Wen-Sin Liew, Libin Yao, Yong Lian
Epilepsy is one of the most common neurological disorders and affects more than 50 million individuals worldwide. Neurosurgery is an option for patients and intracranial EEG monitoring needs to be performed before surger
ISSCC 2010 Session 6 Medical & Bio
A Timing Controlled AC-DC Converter for Biomedical Implants Kim Fung Edward Lee
Alfred Mann Foundation, Santa Clarita, CA, Many biomedical implants are powered from an external magnetic source [1, 2].
The magnetic source is inductively coupled to a coil inside the implant to induce an AC voltage, which is then further rectified to a DC voltage [1]. In general, higher supply voltages are often required for analog circu
ISSCC 2010 Session 6 Medical & Bio
A CMOS Electrochemical Impedance Spectroscopy Biosensor Array for Label-Free Biomolecular Detection
University of Texas, Austin, TX, Biosensors are one of the fundamental detection platforms in biotechnology.
They take advantage of unique biomolecular interactions to capture and detect specific analytes on a surface. The detection versatility of biosensors has always been their key advantage and it has been demonstrated that
ISSCC 2010 Session 7 Other
A 3V 6b Successive-Approximation ADC Using Complementary Organic Thin-Film Transistors on Glass
Wei Xiong1, Ute Zschieschang2, Hagen Klauk2, Boris Murmann1, 1
electronics that can mechanically flex, span large areas, and integrate with polymeric materials. Potential applications include flexible displays, biochemical sensors, and artificial skin. In many applications, OTFTs ac
ISSCC 2010 Session 7 Other
Fully Depleted Extremely Thin SOI for Mainstream 20nm Low-Power Technology and Beyond
Ali Khakifirooz1, Kangguo Cheng1, Basanth Jagannathan2,
Pranita Kulkarni1, Jeffrey W. Sleight3, Davood Shahrjerdi3, Josephine B. Chang3, Sungjae Lee4, Junjun Li4, Huiming Bu1, Robert Gauthier4, Bruce Doris1, Ghavam Shahidi3 1 IBM, Albany, NY, IBM, Hopewell Junction, NY, IBM T
ISSCC 2010 Session 7 Other
An Analog Organic First-Order CT ΔΣ ADC on a Flexible Plastic Substrate with 26.5dB Precision
Hagen Marien1, Michiel Steyaert1, Nick van Aerle2, Paul Heremans1,3, 1
K.U. Leuven, Leuven, Belgium Polymer Vision, Eindhoven, Netherlands 3 IMEC, Heverlee, Belgium 2 Organic electronics is expected to find commercial applications in flexible displays, RFID tags and smart sensor systems, e.
ISSCC 2010 Session 7 Other
User Customizable Logic Paper (UCLP) with Organic Sea-of-Transmission-Gates (SOTG) Architecture and Ink-Jet Printed Interconnects
Koichi Ishida1, Naoki Masunaga1, Ryo Takahashi1, Tsuyoshi Sekitani1,
Shigeki Shino2, Ute Zschieschang3, Hagen Klauk3, Makoto Takamiya1, Takao Someya1, Takayasu Sakurai1 1 University of Tokyo, Tokyo, Japan Mitsubishi Paper Mills, Kyoto, Japan 3 Max Planck Institute for Solid-State Research
ISSCC 2010 Session 7 Other
Robust Digital Design in Organic Electronics by Dual-Gate Technology
Kris Myny1,2,5, Monique J. Beenhakkers3, Nick A. J. M. van Aerle3,
Gerwin H. Gelinck4, Jan Genoe1,5, Wim Dehaene1,2, Paul Heremans1,2 IMEC, Leuven, Belgium, K.U. Leuven, Leuven, Belgium, 3 Polymer Vision, Eindhoven, Netherlands, 4 TNO Science and Industry, Eindhoven, Netherlands, 5 Kath
ISSCC 2010 Session 7 Other
An Integrated Organic Circuit Array for Flexible Large-Area Temperature Sensing
David Da He, Ivan A. Nausieda, Kyungbum Kevin Ryu,
Akintunde I. Akinwande, Vladimir Bulovic, Charles G. Sodini Massachusetts Institute of Technology, Cambridge, MA Traditionally, several technologies have been used for temperature sensing, including integrated silicon ΔV
ISSCC 2010 Session 7 Other
Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing
Mutsuo Daito1, Yoshiro Nakata1, Satoshi Sasaki1, Hiroyuki Gomyo1,
Hideki Kusamitsu1, Yoshio Komoto1, Kunihiko Iizuka1, Katsuyuki Ikeuchi2, Gil Su Kim2, Makoto Takamiya2, Takayasu Sakurai2 1 Association of Super-Advanced Electronics Technologies, Yokohama, Japan University of Tokyo, Tok
ISSCC 2010 Session 7 Other
A Wafer-Level Heterogeneous Technology Integration for Flexible Pseudo-SoC
Hiroshi Yamada, Yutaka Onozuka, Atsuko Iida, Kazuhiko Itaya, Hideyuki Funaki
implemented for monolithic integrated System on Chip (SoC) by applying the advantages of process compatibility between MEMS and CMOS LSI [1]. However, it has been impossible to integrate them in the case that MEMS and st
ISSCC 2010 Session 7 Other
Design Issues and Considerations for Low-Cost 3D TSV IC Technology
Geert Van der Plas1, Paresh Limaye1, Abdelkarim Mercha1,
Herman Oprins1, Cristina Torregiani1, Steven Thijs1, Dimitri Linten1, Michele Stucchi1, Katti Guruprasad1, Dimitrios Velenis1, Domae Shinichi2, Vladimir Cherman1, Bart Vandevelde1, Veerle Simons1, Ingrid De Wolf1, Riet L
ISSCC 2010 Session 7 Other
Demonstration of Integrated Micro-ElectroMechanical Switch Circuits for VLSI Applications
Fred Chen1, Matthew Spencer2, Rhesa Nathanael2, Chengcheng Wang3,
Hossein Fariborzi1, Abhinav Gupta2, Hei Kam2, Vincent Pott2, Jaeseok Jeon2, Tsu-Jae King Liu2, Dejan Markovic3, Vladimir Stojanovic1, Elad Alon2 Massachusetts Institute of Technology, Cambridge, MA, University of Califor
ISSCC 2010 Session 8 Wireline I/O
A 47×10Gb/s 1.4mW/(Gb/s) Parallel Interface in 45nm CMOS
Frank O’Mahony, Joseph Kennedy, James E. Jaussi,
reflects the growing need for lower-power chip-to-chip interfaces for computing systems. Boardlevel transceivers using a variety of low-power circuit techniques have demonstrated power efficiencies as low as 2.2mW/(Gb/s)
ISSCC 2010 Session 8 Wireline I/O
A 6.8mW 7.4Gb/s Clock-Forwarded Receiver with up to 300MHz Jitter Tracking in 65nm CMOS
Masum Hossain, Anthony Chan Carusone
High density multilink interfaces such as QPI and HyperTransport include a dedicated link to carry a synchronous clock from the transmitter to receiver and shared by 5 - 20 data transceivers. Sub-rate clocks ameliorate j
ISSCC 2010 Session 8 Wireline I/O
A 4.5mW/Gb/s 6.4Gb/s 22+1-Lane SourceSynchronous Link RX Core with Optional Cleanup PLL in 65nm CMOS
Robert Reutemann1, Michael Ruegg1, Fran Keyser2, John Bergkvist2,
Rüeschlikon, Switzerland 2 Source synchronous links are often used in server systems for multi-lane highspeed serial applications such as connecting CPU to CPU, to memory, or to bridge chips due to their inherent trackin
ISSCC 2010 Session 8 Wireline I/O
A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS
Hideyuki Sugita, Kazuhisa Sunaga, Koichi Yamaguchi, Masayuki Mizuno
Much effort has been made toward producing a high-speed multi-tap decision feedback equalizer (DFE), which would be a key component in removing intersymbol interference (ISI) in high-speed chip-to-chip communication. A l
ISSCC 2010 Session 8 Wireline I/O
A 12Gb/s 39dB Loss-Recovery Unclocked-DFE Receiver with Bi-dimensional Equalization
Massimo Pozzoni1, Simone Erba1, Davide Sanzogni1, Marcello Ganzerli2,
Reggio Emilia, Modena, Italy 3 University of Pavia, Pavia, Italy 2 Backplane communications are rapidly moving beyond 10 Gb/s both in networking and in hard-disk drive interconnection. Decision Feedback Equalization (DFE
ISSCC 2010 Session 8 Wireline I/O
A Fractional-Sampling-Rate ADC-Based CDR with Feedforward Architecture in 65nm CMOS
Oleksiy Tyshchenko1, Ali Sheikholeslami1, Hirotaka Tamura2,
CDRs take digital samples of the received signal to recover the clock and data. Digital representation of the signal allows for extensive channel equalization in the digital domain. Recently-reported ADC-based CDRs sampl
ISSCC 2010 Session 8 Wireline I/O
A 5Gb/s Transceiver with an ADC-Based Feedforward CDR and CMA Adaptive Equalizer in 65nm CMOS
Hisakatsu Yamaguchi1, Hirotaka Tamura1, Yoshiyasu Doi1,
Yasumoto Tomita1, Takayuki Hamada1, Masaya Kibune1, Shuhei Ohmoto2, Keita Tateishi2, Oleksiy Tyshchenko3, Ali Sheikholeslami3, Tomokazu Higuchi2, Junji Ogawa1, Tamio Saito1, Hideki Ishida4, Kohtaroh Gotoh4 1 Fujitsu Labo
ISSCC 2010 Session 8 Wireline I/O
A 20Gb/s 40mW Equalizer in 90nm CMOS Technology
Sameh A Ibrahim, Behzad Razavi
In order to reduce the pin count of chips and the complexity of the routing on printed-circuit boards and backplanes, it is desirable to replace a large number of parallel channels with a few serial links. Such a transfo