ISSCC 2010
Session 22
Image Sensors
A QVGA 143dB Dynamic Range Asynchronous Address-Event PWM Dynamic Image Sensor with Lossless Pixel-Level Video Compression
Conventional image/video sensors acquire visual information from a scene in time-quantized fashion at some predetermined frame rate. Each frame carries the information from all pixels, regardless of whether or not this i
ISSCC 2010
Session 22
Image Sensors
A CMOS Image Sensor for 10Mb/s 70m-Range LEDBased Spatial Optical Communication
recently been of interest in the mobile localarea communication systems, especially in the automotive applications. It has many advantages over the radio communication such as robustness to jamming, human safety due to l
ISSCC 2010
Session 22
Image Sensors
A 256×256 14k Range Maps/s 3-D Range-Finding Image Sensor Using Row-Parallel Embedded Binary Search Tree and Address Encoder
These days, 3-D information technology is being developed rapidly and has been applied to various fields. Moreover, ultra-fast 3-D range-finding makes way for the possibilities of additional applications such as drop tes
ISSCC 2010
Session 22
Image Sensors
An 80×60 Range Image Sensor Based on 10µm 50MHz Lock-In Pixels in 0.18µm CMOS
provided by standard digital cameras is often not sufficient to build the sophisticated models required by systems capable of analyzing and interpreting their environment. A three-dimensional (3D) image sensor has great
ISSCC 2010
Session 22
Image Sensors
A 2.2/3-inch 4K2K CMOS Image Sensor Based on Dual Resolution And Exposure Technique
from HD to 4K2K, which will further extend to 8K4K / portable 4K2K. With advancements in device fabrication process technologies, there has been a pressing need for the miniaturization as well as high resolution and high
ISSCC 2010
Session 22
Image Sensors
A 1/2.3-inch 10.3Mpixel 50frame/s Back-Illuminated CMOS Image Sensor
Souichiro Kuramochi1, Oichi Kumagai1, Seijiro Sakane1, Masamichi Ito1, Masahiro Hatano1, Masaru Kikuchi1, Yuuki Yamagata1, Takeshi Shikanai1, Ken Koseki1, Keiji Mabuchi1, Yasushi Maruyama1, Kentaro Akiyama1, Eiji Miyata2
ISSCC 2010
Session 23
mm-Wave
A Millimeter-Wave Intra-Connect Solution
Hidenori Takeuchi1, Tomoari Itagaki1, Yasufumi Hino1, Yoshinobu Kawasaki1, Katsuhisa Ito1, Ali Hajimiri2 Sony, Tokyo, Japan, California Institute of Technology, Pasadena, CA Figure 23.1.4 shows the measured injection loc
ISSCC 2010
Session 23
mm-Wave
A SiGe Quadrature Transmitter and Receiver Chipset for Emerging High-Frequency Applications at 160GHz
A chipset for emerging high-frequency applications at 158 to 165GHz is presented. The two chips (RX and TX) are implemented in a European (DotFive) SiGe BiCMOS technology with fT=260GHz and fMAX=380GHz [1]. Envisioned ap
ISSCC 2010
Session 23
mm-Wave
A W-Band 65nm CMOS Transmitter Front-End with 8GHz IF Bandwidth and 20dB IR-Ratio
The nanoscale era of CMOS technology has enabled the integration of mm-Wave circuits and front-ends at W-band [1,2]. The possible applications range from telecommunications (71 to 76 & 81 to 86GHz) and collision avoidanc
ISSCC 2010
Session 23
mm-Wave
A 90GHz-Carrier 30GHz-Bandwidth Hybrid Switching Transmitter with Integrated Antenna
STMicroelectronics, Crolles, France 2 There is considerable interest in wideband pulse modulation at mm-Wave frequencies for application in radar and medical imaging systems [1,2]. Accuracy and resolution in these respec
ISSCC 2010
Session 23
mm-Wave
A 13.1% Tuning Range 115GHz Frequency Generator Based on an Injection-Locked Frequency Doubler in 65nm CMOS
University of Modena and Reggio Emilia, Modena, Italy Istituto Universitario di Studi Superiori, Pavia, Italy 3 STMicroelectronics, Pavia, Italy 4 University of Pavia, Pavia, Italy 2 Ultra-scaled CMOS devices offer the p
ISSCC 2010
Session 23
mm-Wave
A 1V 17.9dBm 60GHz Power Amplifier in Standard 65nm CMOS
J. Watson, Yorktown Heights, NY 2 For point-to-point multi-Gb/s applications in mobile devices with single antennas, low-cost, highly integrated solutions are preferred, and CMOS technology is a candidate for mm-Wave SoC
ISSCC 2010
Session 23
mm-Wave
A High-Gain 60GHz Power Amplifier with 20dBm Output Power in 90nm CMOS
input matching network of the second stage is matched with 50Ω to minimize loss while the output matching network is designed to deliver maximum output power using power contours which were determined by load-pull simula
ISSCC 2010
Session 23
mm-Wave
A 53-to-68GHz 18dBm Power Amplifier with an 8-Way Combiner in Standard 65nm CMOS
been demonstrated to satisfy the market demand for high data rates and frequency bandwidths [1-6]. However, 60GHz products need an improvement in power performance as well as transistor reliability for large signal opera
ISSCC 2010
Session 23
mm-Wave
A 650GHz SiGe Receiver Front-End for Terahertz Imaging Arrays
Terahertz (300GHz-to-3THz) imaging systems and radars are capable of providing high resolution images while still penetrating many materials [1]. Imaging receivers based on III-V Schottky diodes and waveguide technology
ISSCC 2010
Session 24
Memory
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns Bank-to-Bank Active Time and No Bank-Group Restriction
Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang,
ISSCC 2010
Session 24
Memory
Paper withdrawn by author • 2010 IEEE International Solid-State Circuits Conference 978-1-4244-6034-2/10/$26.00 ©2010 IEEE
ISSCC 2010
Session 24
Memory
An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR Inductive-Coupling Interface Between 65nm CMOS GPU and 0.1µm DRAM
This paper presents an 8Tb/s 1pJ/b 0.8mm2/Tb/s quad data rate (QDR) inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM. The interface consists of 1024-bit parallel inductive-coupling transceivers operating
ISSCC 2010
Session 24
Memory
A Bitline Sense Amplifier for Offset Compensation
DRAM chips [1]. To satisfy this need, it is desirable to use a low VCORE in the DRAM core, even though with such a low voltage it is difficult to sense the cell signal due to an insufficient sensing margin in high densit
ISSCC 2010
Session 24
Memory
A 2Gb/s 1.8pJ/b/chip Inductive-Coupling ThroughChip Bus for 128-Die NAND-Flash Memory Stacking
NAND Flash memory chips and 1 controller chip are stacked in a single package for SSD applications (Fig. 24.5.1). The controller chip accesses a random memory chip by relayed transmission using inductive-coupling transce
ISSCC 2010
Session 24
Memory
A 159mm2 32nm 32Gb MLC NAND-Flash Memory with 200MB/s Asynchronous DDR Interface
Kwon, Chulbum Kim, Younyeol Lee, Sangsoo Park, Kyungmin Kim, Doohyun Cho, Juseok Lee, Jungho Song, Soowoong Lee, Hyukjun Yoo, Sanglok Kim, Seungwoo Yu, Sungjun Kim, Sungsoo Lee, Kyehyun Kyung, Yong-Ho Lim, Chilhee Chung
ISSCC 2010
Session 24
Memory
A 3bit/Cell 32Gb NAND Flash Memory at 34nm with 6MB/s Program Throughput and with Dynamic 2b/Cell Blocks Configuration Mode for a Program Throughput Increase up to 13MB/s
C. Lattaro1, C. Musilli1, D. Rivers2, E. Sirizotti1, F. Paolini1, G. Imondi1, G. Naso1, G. Santin1, L. Botticchio1, L. De Santis1, L. Pilolli1, M.L. Gallese1, M. Incarnati1, M. Tiburzi1, P. Conenna1, S. Perugini1, V. Mos
ISSCC 2010
Session 24
Memory
A 32Gb MLC NAND-Flash Memory with Vth-EnduranceEnhancing Schemes in 32nm CMOS
Park, Yongdeok Cho, Chaekyu Jang, Chulwoo Yang, Sanghwa Chung, InSuk Yun, Byoungin Joo, Byoungkwan Jeong, Jeeyul Kim, Jaekwan Kwon, Hyunjong Jin, Yujong Noh, Jooyun Ha, Moonsoo Sung, Daeil Choi, Sanghwan Kim, Jeawon Choi
ISSCC 2010
Session 25
Wireless
A Maximally-Digital Radio Receiver Front-End Frank Opteynde
analog circuits content in radio transmitters and synthesizers, in favour of more digital circuits. But for radio receivers, a major amount of analog circuitry is still required [1,3]. This paper demonstrates the feasibi
ISSCC 2010
Session 25
Wireless
A 65nm CMOS 2.4GHz 31.5dBm Power Amplifier with a Distributed LC Power-Combining Network and Improved Linearization for WLAN Applications
greatest challenges facing the designers of complex wireless SoCs. Recently, there has been a significant effort to implement PA’s in CMOS [1-4]. The 802.11g standard utilizes OFDM modulation, which has a very high peak-
ISSCC 2010
Session 25
Wireless
A Fully Integrated 2×1 Dual-Band Direct-Conversion Transceiver with Dual-Mode Fractional Divider and Noise-Shaping TIA for Mobile WiMAX SoC in 65nm CMOS nent, 1/3 fC, is actually generated by the mismatch at the output, its power level is low enough to be filtered out by the subsequent circuits, as is the case for the “fractional-then-distribute” architecture with LC-BPFs. This issue is less critical in RX.
Masaomi Iwanaga, Kenichi Sami, Rui Ito, Junji Wadatsumi, Yuki Tsuda, Shoko Oda, Shunji Kawaguchi, Nobuyuki Itoh, Mototsugu Hamada Figure 25.4.4 shows the measured spurs at the TX output. Other than 1/3 fC, 2/3, 4/3, and
ISSCC 2010
Session 25
Wireless
A 5mm2 40nm LP CMOS 0.1-to-3GHz Multistandard Transceiver
Bjorn Debaillie1, Peter Van Wesemael1, Tomohiro Sano2, Takaya Yamamoto3, Dries Hauspie4, Joris Van Driessche1, Jan Craninckx1 quency was therefore limited to 3GHz. The differential mixer’s gain can be lowered over 12dB i
ISSCC 2010
Session 25
Wireless
A Multistandard Multiband Mobile TV RF SoC in 65nm CMOS
Jungwook Heo, Sanghoon Kang, Jong-Dae Bae, Heetae Oh, Youngwoon Kim, Taek-Won Kwon, Ryan Kim, Wooseung Choo, Dojun Rhee, Byeong-ha Park Samsung Electronics, Yongin, Korea The mobile TV applications such as DVH-H/T, T-DMB
ISSCC 2010
Session 25
Wireless
A 1V RF SoC with an 863-to-928MHz 400kb/s Radio and a 32b Dual-MAC DSP Core for Wireless Sensor and Body Networks
Patrick Volet, Daniel Sigg, Pascal Heim, Jean-Félix Perotto, François Kaess, Nicolas Raemy, Alexandre Vouilloz, David Ruffieux, Matteo Contaldo, Frédéric Giroud, Daniel Séverac, Marc Morgan, Stève Gyger, Cédric Monneron,
ISSCC 2010
Session 26
Digital Circuits
A 3.5GHz Wideband ADPLL with Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation
Columbia University, New York, NY University of Pavia, Pavia, Italy 3 STMicroelectronics, Pavia, Italy 2 The digital-intensive approach to frequency synthesis embodied by the ADPLL
ISSCC 2010
Session 26
Digital Circuits
A 2.1-to-2.8GHz All-Digital Frequency Synthesizer with a Time-Windowed TDC
NEC, Kawasaki, Japan NEC Electronics, Kawasaki, Japan 2 All-digital phase-locked loops (ADPLLs) offer the advantages of eliminating the large on-chip passive filter and not suffering from poor low-supply-voltage operatio
ISSCC 2010
Session 26
Digital Circuits
A Calibration-Free 800MHz Fractional-N Digital PLL with Embedded TDC
Atheros Communications, Santa Clara, CA Digital Phase-Locked Loops (DPLLs), which are amenable to CMOS process scaling, have recently been demonstrated for both wireless and wireline applications as alternatives to conve
ISSCC 2010
Session 26
Digital Circuits
Spur-Reduction Techniques for PLLs Using SubSampling Phase Detection
University of Twente, Enschede, Netherlands National Semiconductor, Santa Clara, CA 2 In PLL designs, a wide loop bandwidth is often desired as it offers fast settling time, reduces on-chip loop filter area and sensitivi
ISSCC 2010
Session 26
Digital Circuits
A 3MHz-BW 3.6GHz Digital Fractional-N PLL with
spurs [1], [2]. However, the actual results depend dramatically on the linearity of the time-to-digital converter (TDC). This paper presents a 3MHz bandwidth fractional-N synthesizer, which combines a 4ps TDC with digita
ISSCC 2010
Session 26
Digital Circuits
A 1.4psrms-Period-Jitter TDC-Less Fractional-N Digital PLL with Digitally Controlled Ring Oscillator in 65nm CMOS
State of the art digital PLLs can be divided in two categories, depending on the implementation of the digital phase detector. Digital clocking and wireline applications mostly use a Bang-Bang detector (BBPLLs) [1-3], of
ISSCC 2010
Session 26
Digital Circuits
A 86MHz-to-12GHz Digital-Intensive PhaseModulated Fractional-N PLL Using a 15pJ/Shot 5ps TDC in 40nm digital CMOS
IMEC, Leuven, Belgium K.U. Leuven, Leuven, Belgium 2 Digital-intensive PLL architectures emerge [1]-[4], exploiting the benefits of CMOS scaling. This work presents a digital-intensive, reconfigurable 86MHz12GHz synthesi
ISSCC 2010
Session 26
Digital Circuits
A 1GHz ADPLL with a 1.25ps Minimum-Resolution Sub-Exponent TDC in 0.18µm CMOS
since the minimum resolvable time quantity is proportional to one-inverter delay [1]. For fine time resolution, vernier delay chains are frequently used [2,3]. Since the time resolution is determined by the difference be
ISSCC 2010
Session 27
RF & Wireless
A Batteryless Thermoelectric Energy-Harvesting Interface Circuit with 35mV Startup Voltage
Energy harvesting is an emerging technology with applications to handheld, portable and implantable electronics. Harvesting ambient heat energy using thermoelectric generators (TEG’s) [1] is a convenient means to supply
ISSCC 2010
Session 27
RF & Wireless
Nano-Watt Power Management and Vibration Sensing on a Dust-Size Batteryless Sensor Node for Ambient Intelligence Applications
preventing the realization of dust-size battery-less sensor nodes are reported. Sensor networks deploying large numbers of nodes are anticipated for “ambient intelligence” [1]. For such networks, the sensor nodes should
ISSCC 2010
Session 27
RF & Wireless
Palm NMR and One-Chip NMR 1 2 2 1
Cambridge, MA, T2 Biosystems, Cambridge, MA 2 3 Nuclear magnetic resonance, or NMR, is the energy exchange between an RF magnetic field and an atomic nucleus such as a hydrogen proton, which is a tiny bar magnet due to i
ISSCC 2010
Session 27
RF & Wireless
A 3.9mW 25-Electrode Reconfigured Thoracic Impedance/ECG SoC with Body-Channel Transponder
cardiovascular-related disease [1] with wearable body sensor network (WBSN) [2-3]. The WBSN introduced in [3] monitored ECG at maximum 48 points, and transferred data using arrayed inductive link for cm-range wireless in
ISSCC 2010
Session 27
RF & Wireless
A Multichannel DNA SoC for Rapid Point-of-Care Gene Detection
Samuel Reed, Leila M Shepherd, Winston Wong Jr, K.T. Lim, Christofer Toumazou DNA Electronics, London, United Kingdom Point-of-care diagnostics for detection of genetic sequences require biosensing platforms that are sen
ISSCC 2010
Session 27
RF & Wireless
A Single-Inductor AC-DC Piezoelectric EnergyHarvester/Battery-Charger IC Converting ±(0.35 to 1.2V) to (2.7 to 4.5V)
Microscale integration constrains energy and the lifetime microsystems like wireless sensors and biomedical implants can achieve to impractical levels. Harnessing ambient vibration energy from a small piezoelectric trans
ISSCC 2010
Session 27
RF & Wireless
A 110µW 10Mb/s eTextiles Transceiver for Body Area Networks with Remote Battery Power
Emerging sensor technologies are enabling low-cost ambulatory medical devices for remote patient monitoring. In order to replace traditional bulky wired links used to communicate data around and away from the body, recen
ISSCC 2010
Session 27
RF & Wireless
A 5.4dBm 42mW 2.4GHz CMOS BAW-Based QuasiDirect Conversion Transmitter
The trend of low-data rate wireless sensor networks (WSN) to interface at higher data rate with other devices or networks using standard protocols such as Bluetooth Low Energy and ZigBee, calls for a flexible RF system a
ISSCC 2010
Session 27
RF & Wireless
An 8.6GHz 42ps Pulse-Width Electrical Mode-Locked Oscillator
This paper reports on a fully integrated electrical mode-locked oscillator. Modelocked oscillators are traveling wave oscillators that excite multiple spectral modes of a transmission line resonator and lock them in phas
ISSCC 2010
Session 27
RF & Wireless
Ultra-Low-Voltage Circuits for Sensor Applications Powered by Free-Space Optics
University of California, Davis, CA Cisco Systems, Davis, CA 3 Agilent Technology, Santa Clara, CA 2 Advances in photonics have typically been exploited in high performance systems, e.g. high-frequency, low-jitter clocks
ISSCC 2010
Session 3
RF & Wireless
A Quad-Band Class-39 RF CMOS Receiver for Evolved EDGE
polarize between high-end smart phones and ultra-low-cost devices, with the former providing the only growth sector during the downturn recently. A key enabler for the popular smart phones, netbooks and other mobile broa
ISSCC 2010
Session 3
RF & Wireless
A 0.8mm2 All-Digital SAW-Less Polar Transmitter in 65nm EDGE SoC
Khurram Waheed1, Mitch Entezari1, Gennady Feygin1, Sudheer Vemulapalli1, Vasile Zoicas1, Chih-Ming Hung1, Nathen Barton1, Imran Bashir1, Kenneth Maggio1, Michel Frechette1, Meng-Chang Lee1, John Wallberg1, Patrick Cruise
ISSCC 2010
Session 3
RF & Wireless
A Tri-Band SAW-Less WCDMA/HSPA RF CMOS Transceiver with On-Chip DC-DC Converter Connectable to Battery
Thomas Burger2, Thomas Christen1, Dimitris Papadopoulos1,4, Ilian Kouchev1, Chiara Martelli1,2, Thomas Dellsperger1 1 Advanced Circuit Pursuit, Zollikon, Switzerland ETH Zürich, Zürich, Switzerland, 3 now with Marvell Se