2011

Taishi Takasawa1, Tomoyuki Akahori2, Keigo Isobe2, Takashi Watanabe2, Shinya Itoh1, Shoji Kawahito1,2 1 Shizuoka University, Hamamatsu, Japan, Brookman Technology, Hamamatsu, Japan, 3 Sanei Hytechs, Hamamatsu, Japan 2 Lo

Toshiaki Sato2, Tim Bales3, Katsuyuki Kawamura2, Eduard Pages2, Shinichiro Matsuo2, Tetsuji Kawaguchi2, Tadashi Sugiki2, Norio Yoshimura2, Junichi Nakamura2, John Ladd1, Zhiping Yin1, Russell Iimura1, Xiaofeng Fan1, Scot

Hiroyuki Iwaki1, Yuji Gendai1, Hirotaka Murakami1, Kenichi Takamiya2, Hiroshi Shiroshita1, Yoshinori Muramatsu1, Toshihiro Furusawa1 1 Sony, Kanagawa, Japan, Sony LSI Design, Kanagawa, Japan 2 Recently, the demands to ac

CSEM, Zurich, Switzerland, 3 CSEM, Landquart, Switzerland, 4 EPFL, Neuchâtel, Switzerland The conversion factor used to calculate the equivalent noise charge is determined by a photon transfer curve measurement. Investig

cooled Infrared (IR) HgCdTe (Mercury Cadmium Telluride) hybrid sensors (detector bump-bounded over the CMOS IC) are very demanding in term of SNR (typical state-of-the-art values are in the 70to-80dB range [1,2]). Consid

Masatoshi Tanaka1, Kohsei Takehara1, Tomoo Okinaka1, Harry van Kuijk2, Wilco Klaassens2, Jan Bosiers2, Michael Lesser3, David Ouellette3, Hirotaka Maruyama4, Tetsuya Hayashida4, Toshiki Arai4 1 Kinki University, Higashi-

Masato Fujita, Satoshi Hirayama, Taikan Kanou, Sakae Hashimoto, Genzo Momma, Shunsuke Inoue Canon, Kawasaki, Japan Large-format image sensors provide us with a new form of vision in several areas such as astronomy and in

University of Edinburgh, Edinburgh, United Kingdom, STMicroelectronics, Edinburgh, United Kingdom Low-cost 3D image capture devices are enabling new applications in the gaming, robotics, automotive and surveillance indus

Conventional cameras capture 2D photographs at a single plane of focus. Acquisition of a 3D photograph with multiple planes of focus typically requires scanning the focus of a single camera [1], or using arrays of camera

T. Willassen1, S. Skaug1, T. Martinussen1, D. Whittlesea2, G. Ali3, J. Ladd3, X. Li3, S. Johnson3, V. Rajasekaran3, Y. Lee4, J. Bai3, M. Flores3, G. Davies2, H. Samiy2, A. Hanvey2, D. Perks2 1 Aptina, Oslo, Norway, Aptin

Younghwan Park1, Taesub Jung1, Youngheup Jang1, Bumsuk Kim1, Yitae Kim1, Shay Hamami2, Uzi Hizi2, Mickey Bahar2, Changrok Moon1, JungChak Ahn1, Duckhyung Lee1, Hiroshige Goto1, Yun-Tae Lee1 1 Samsung Electronics, Yong-In

digital devices such as cameras, media players and high-definition TVs has seen a significant growth. This requires tuners for home networking such as MoCA with increasingly large bandwidth. Though advanced CMOS technolo

Intel, Hillsboro, OR As CMOS technology continues to scale for SoC applications, significant challenges to implement a monolithic linear high-power amplifier have emerged. This results from the low breakdown voltage of t

Wireless high-speed communication standards such as WiFi, WiMax and LTE use spectrally-efficient OFDM modulation that encodes signal information in both amplitude and phase. Use of this non-constant envelope modulation r

Samsung Electro-Mechanics, Atlanta, GA Although Si CMOS PAs for mobile applications have demonstrated specificationcompliant performance over the last several years, Si CMOS has not been widely employed in cellular PA ap

One of the remaining challenges in implementing CMOS 60GHz radios is to cover longer communication distance as the high path loss at mm-Wave frequencies demands higher EIRP, which in turn requires considerable design eff

For this PD, a triangular waveform is the ideal waveform as its interpolated zerocrossings coincide with the actual zero-crossings. Figure 25.1.3 shows how the amplitude of the desired waveform is generated. Two adjacent

acquisition range offer flexibility in optical communication networks, help reduce link power through activity-based rate adaptation, and minimize cost with a single-chip multi-standard solution. Extracting the bit rate

A clock and data recovery (CDR) circuit is the key building block in all serial communication systems. A classical CDR is implemented using a Type-2 phaselocked loop (PLL) wherein a passive lead-lag analog loop filter is

Seong-Ho Lee1, Hamid Hatamkhani1, Mario Caresosa1, Karo Khanoyan1, Haitao Tong1, Duke Tran1, Anthony Brewster1, Ichiro Fujimori1 1 2 Broadcom, Irvine, CA Broadcom, Austin, TX It has been well understood that the digital

As data rates increase, the backplane communication systems suffer from serious inter-symbol interference (ISI). Due to different channel lengths, loss, and environment variations, an adaptive equalizer is an attractive

The increasing demand for high-bandwidth interconnection between integrated circuits requires large numbers of I/Os per chip as well as high data rates per I/O. Key limitations in meeting these requirements include chann

Netlogic Microsystems, Santa Clara, CA Two commercially important standards for 10Gb/s serial data transfer include the SFI specification, associated with SFP+ optical modules and copper twinaxial cable [1], and the 10GB

As the panel technology continues to offer displays with higher resolution, greater color depth, and increased frame rate, the amount of video data to display driver ICs (DDIs) inside the panel keeps on expanding. Since

Hartwig Unterassinger1, Günter Hofer2, Michael Klamminger1, Wolfgang Pribyl1, Gerald Holweg2 1 2 Graz University of Technology, Graz, Austria, Infineon Technologies, Graz, Austria The combination of remote powering and w

research on how to guarantee a reliable RX performance under simultaneous TX/RX operation. To isolate RX from the TX self-jammer, the RFID transceivers are generally accompanied by an off-chip circulator or isolator. Thi

Simonetta Rampu1, Cui Zhou1, Li Huang1, Koji Imamura2, Ben Busze1, Frank Bouwens1, Mario Konijnenburg1, Juan Santana1, Arjan Breeschoten1, Jos Huisken1, Guido Dolmans1, Harmke de Groot1 1 2 Holst Centre / imec, Eindhoven

For true low-power peer-to-peer wireless links for sensing, link symmetry must be maintained unlike in [1,2] where the burden is shifted to the receiver. In addition, the transceiver power dissipation and performance sho

Kuan-I Li1, Jui-Lin Hsu1, Chi-Lun Lo1, Hsin-Hua Chen1, Sheng-Yuan Su1, Kun-Tso Chen1, Min Chen1, Osama Shana’a2, Shu-Hung Chou1, George Chien3 1 3 MediaTek, Hsinchu, Taiwan, 2MediaTek, Singapore, Singapore, MediaTek, San

Extensive research has been focused on generating LO signals for softwaredefined radios (SDRs) with ultra-wide tuning range over several frequency decades and sufficiently high spectrum purity to support diverse wireless

University of California, Los Angeles, CA, Oracle, Menlo Park, CA 2 Multiplying delay-locked loops (MDLLs) [1-5] have been shown to have improved jitter accumulation and tracking over VCO-based PLLs. By injecting the ref

2 NXP Semiconductors, Eindhoven, The Netherlands Delft University of Technology, Delft, The Netherlands In this paper, a high-speed continuous-time (CT) ΔΣ ADC topology is proposed that absorbs the pole normally caused b

There is ongoing effort to realize low-power ΔΣ ADCs with more than 10MHz bandwidth (BW) – especially for wireless transceivers. Besides the trend to make these ADCs more reconfigurable [1], recent advances in the design

The aspirations for power efficient ADCs have led to many improvements in this area. In delta-sigma modulators, techniques such as VCO-based quantizer [1, 2] and time-domain quantization [3] have been proposed to enhance

One of the most continuous trends in solid-state circuits is the decrease in power supply as a direct consequence of technology scaling. The fact that Vt does not scale linearly with supply voltage has encouraged several

This third-order ΔΣ modulator [1, 2], suitable for high-resolution low-power sensor systems, consumes 140µW to obtain 84dB SNDR with OSR=16 and 100kHz signal bandwidth. The achieved FoM is 54fJ/conversion-step The DACs u

SCK-CEN, Mol, Belgium 3 KH Kempen, Geel, Belgium The frequency of the relaxation oscillator can be expressed as IREF/(VREF·2C). By correlating VREF and IREF as VREF = IREF·R, its frequency becomes only dependant on passi

Analog Devices, Wilmington, MA Automotive and consumer multi-channel 24b audio systems have demanded low-cost digital-to-analog converters (DACs) which offer wide dynamic range, high linearity, small die size, and low po

fine-resolution quantization to reduce the out-of-band noise (OBN), reduce jitter sensitivity, and simplify analog filtering. Recent techniques achieve this goal by using a mix of DAC elements with different weights, e.g

all-digital PLL (ADPLL) [1] for Bluetooth radios has proven benefits of CMOS scaling and integration, demonstrators for more challenging wireless standards have emerged [2-6]. In the ADPLL, however, the digitallycontroll

Advanced deep-submicron CMOS processes are well-suited for a digital implementation of phase-locked loop-(PLL) based frequency synthesizers. Recently, several RF all-digital phase-locked loops (ADPLL) have been reported

Intel, Hillsboro, OR Process scaling enables SoC integration of radio and large digital systems at reduced cost and area. Furthermore, the crowded spectrum requires high linearity receivers to enable co-existence in the

Melina Apostolidou2, Leo C.N. de Vreede1, Domine Leenaerts2, Jan Sonsky3 1 Delft University of Technology, Delft, The Netherlands, NXP Semiconductors, Eindhoven, The Netherlands, 3 NXP-TSMC Research Center, Leuven, Belgi

low-IF, benefitting from a simple structure, and a high level of integration as image rejection is not a major concern, and channel selection is performed by low-frequency lowpass filters [Fig. 3.5.1(a)]. Dominated by li

reconfigurability to replace any standard radio: they develop toward systems where a simplified antenna interface can be used, with most dedicated filtering removed. This requires a receiver accommodating much higher lin

Frank E. van Vliet1,2 1 University of Twente, Enschede, The Netherlands, TNO Science and Industry, The Hague, The Netherlands 2 Phased-array receivers provide two major benefits over single-antenna receivers

shown in Fig. 3.8.4. Loop Gain of this buffer at the low IF frequency helps to significantly reduce its gain and phase errors. Gains proportional to sine-wave coefficients are set by conductances proportional to sine-wav

M.J. Saccamango2, F. Malgioglio2, P. Meaney2, D. Plass2, Y.-H. Chan2, M. Mayo2, G. Mayer4, L. Sigal5, D. Rude2, R. Averill2, M. Wood2, T. Strach4, H. Smith2, B. Curran2, E. Schwarz2, L. Eisen3, D. Malone2, S. Weitzel3, P

logic functions are making their way onto critical path SRAMs in the L1 cache look up structure. Described in this paper is a 14 bit dynamic hit logic scheme with an embedded 8K bit SRAM in IBM’s 45nm SOI [3]. The hit lo

of 10 Westmere 32nm cores [2] and a shared inclusive L3 cache (LLC) integrated on a monolithic die, with link-based I/Os. This paper focuses on the innovations and circuit optimizations over the predecessor [3] targeting