2011

processor series, the Godson-3B processor is an 8-core high-performance general-purpose processor implemented in 65nm CMOS low-power general-purpose mixed process with 7 layers of Cu metallization. Godson-3B contains 582

Michael Golden2, Scott Hilker2, Aaron Horiuchi1, Kevin A. Hurd1, Dave Johnson1, Hugh McIntyre2, Samuel Naffziger1, James Vinh2, Jonathan White4, Kathryn Wilcox4 instead of a traditional mismatch CAM. The integer datapath

AMD’s two-core Bulldozer module [1,2] implements the AMD x86-64 microarchitecture in an 11-layer 32-nm SOI HKMG technology. The 40-instruction outof-order unified integer scheduler issues up to four operations per cycle

Intel, Santa Clara, CA Within a given power envelope, the performance of a multi-core enterprise processor is greatly affected by inter-core (including I/O) data throughput and data transport latency. This paper presents

named Poulson, has eight multi-threaded 64 bit cores. Poulson is socket compatible with the current Intel® Itanium® Processor 9300 series (Tukwila) [1]. The new design integrates a ring-based system interface derived fro

Carlo Samori, Andrea L. Lacaita Politecnico di Milano, Milan, Italy State-of-the-art digital fractional-N PLLs intended for modern wireless systems make use of high-resolution and high-linearity time-to-digital converter

In modern analog front-ends, there is an increasing demand on high- performance analog-to-digital converters (ADCs), which require high sampling frequency and low-jitter sampling clock. This makes low-jitter phase-locked

viable alternative to classical charge-pump analog PLLs [1-4]. By obviating the need for a large loop filter capacitor and a high-performance charge pump, DPLLs offer area savings and easier scalability to newer processe

In the design of a fractional-N PLL, the trade-off between in-band VCO noise and ΔΣ quantization noise constrains the choice of loop bandwidth. Various circuit schemes have been proposed to relax such constrains with noi

System-on-chips (SoCs) are being widely adopted in mobile applications, and are driven by the need for longer battery life, their power budget continues to decrease. In addition, the phase-locked loop (PLL) for the SoC h

Sampling clock jitter significantly degrades the circuit performance and dynamic range of an ADC [1]. This paper presents a 570fsrms integrated-jitter 1.21GHz PLL with a hybrid loop. A ring VCO has a much inferior phase

more popular as possible alternatives to conventional analog charge-pump-based PLLs [1]. Currently, most of the ADPLLs are based on a time-to-digital converter (TDC) utilizing inverter delay chains. There have been treme

Chebyshev filter and amplified by a variable-gain amplifier (VGA). The VGA gain is automatically tuned by an outer automatic gain control (AGC) loop to regulate and verify the amplitude of the sustained oscillation at th

Tsinghua University, Beijing, China, Delft University of Technology, Delft, The Netherlands 2 This paper describes a smart CMOS wind sensor that measures wind speed and direction without moving parts. It combines a 2-D t

Germany 2 With ongoing miniaturization in technology and increasing complexity in assembly and packaging, stress-sensing microsystems gain importance for the evaluation of IC packages [1]. Additionally, integrated stress

Precision thermocouples and bridge transducers such as strain gauges and thermistors require read-out ICs with low noise, high accuracy and low drift. In such applications, the sensor and the read-out IC (ROIC) are usual

techniques has been developed to satisfy various electrical and electronics applications requirements [1,2]. In high-voltage applications, the main issue is the electrical isolation with accurate measurement at low signa

Vrije Universiteit Brussel, Brussels, Belgium In Fig. 6.6.4 the linear law applies to a voltage step that is 1/20th of the range; the exponential law shown applies to a ratio C2/C1=20. In the real circuit this ratio is 1

–e.g. retinal prostheses [1]– necessitate very low-voltage, low-leakage, and energy-efficient image sensors that preferably produce their own power from ambient sources. A natural energy source for an image sensor that p

Energy harvesting provides a means to supply wireless sensor networks in building environments with autonomous and sustainable power [1,2]. Indoor light can be converted into electricity by a solar cell and stored in a r

Harvesting energy from ambient vibrations is a promising technology for fully autonomous wireless sensor nodes, which can give birth to new applications in biomedical, industrial, and environmental monitoring. There have

Hsin-Jung Yang, Shao-Yi Chien, Li-Fu Ding, Wei-Yin Chen, Chih-Chi Cheng, Tung-Chien Chen, Liang-Gee Chen National Taiwan University, Taipei, Taiwan 3DTV promises to become the mainstream of next-generation TV systems. Hi

Future video decoders will need to support high resolutions such as Quad Full HD (QFHD, 4096×2160) and fast frame rates (e.g. 120fps). Many of these decoders will also reside in portable devices. The next-generation stan

processing, vision, and 3D graphics require high external memory bandwidth. In augmented-reality (AR) processors [1], both 3D graphics and vision operations are required, so memory bandwidth becomes even more critical. I

portable game consoles, and robots for such intelligent applications as object detection, recognition, and human-computer interfaces (HCI). Most of these functions are realized in software with neural networks (NN) and f

J. Gu3, Alice Wang1, Hugh Mair1, Satyendra Datla1, Bing Rong1, Sushma Honnavara-Prasad1, Lam Ho1, Greg Baldwin1, Dennis Buss1, Anantha P Chandrakasan2, Uming Ko1 1 Texas Instruments, Dallas, TX, Massachusetts Institute o

standard for broadband wireless access, known as Worldwide Interoperability for Microwave Access (WiMAX), provides high throughput over long-range transmission. The key developments in the physical (PHY) layer include Or

Ching-Wen Hsueh, Shyuan Liao, Jian-Bang Lin, Shun-An Yang, Chin-Tai Liu, Tsai-Pao Lee, Jin-Ru Chen, Chia-Hua Chou, Min Chen, Den-Kai Juang, Jen-Hao Yeh, Chieh-Wei Liao, Po-Hung Chen, Kaipon Kao, Chia-Hsin Wu, Wen-Tso Hua

A downside for all direct digital synthesizer (DDS) architectures is that every DDS has a phase accumulator (PA) whose normalized phase value φ must be updated for each (sin 2πφ, cos 2πφ) output-pair produced, and such u

Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz Broadcom, Irvine, CA An 11.3Gb/s CMOS SONET-compliant transceiver is designed to work in both RZ a

Teranetics, San Jose, CA A transmitter and echo cancellation hybrid for IEEE 802.3an 10GBase-T Ethernet standard is presented, that utilizes DSP techniques to enhance the linear cancellation, and analog non-linearity can

Next generation optical and electrical communications such as chip-to-chip serial links or 100GbE require very-high-speed transceivers. At tens of Gb/s, both transmitters and receivers suffer from inadequate bandwidth an

Koji Fukuda1, Noboru Masuda1, Ryo Nemoto2, Eiichi Suzuki1, Takashi Takemoto1, Fumio Yuki1, Masayoshi Yagyu1, Hidehiro Toyoda1, Akihiro Kambe1, Tatsuya Saito1, Shinji Nishimura1 1 Hitachi, Tokyo, Japan Hitachi, Ibaraki, J

demand for high-speed, low-cost, and low-overhead I/Os in today’s electronic systems, has been addressed by three general categories of interconnects: electrical, optical, and wireless. The electrical interconnects are t

bandwidth in high performance compute systems is driving the need for energy-efficient multi-Gb/s I/O serial links. Improved power efficiency was demonstrated using adaptive supply regulation [1, 2]. However, power losse

are widely used in passive optical networks (PON) [1] and as a replacement for conventional CDRs in clock-forwarding links to reduce power [2]. In PON, a single CDR performs the task of clock and data recovery for severa

state-of-the-art CMOS technologies makes the design of high-speed transmitters at signaling swings above the typical 1V supply a challenging task. Higher-voltage TX amplitude is not only required in older I/O standards a

Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Ning Li, Shogo Ito, Win Chaivipas, Ryo Minami, Akira Matsuzawa Tokyo Institute of Technology, Tokyo, Japan This paper presents a 60GHz direct-conversion transceive

Christopher Mounet1, Fabrice Chaix1, Romain Ferragut3, Cedric Dehos1, Jerome Lanteri1, Laurent Dussopt1, Silas D. Yamamoto2, Romain Pilard2, Pierre Busson2, Andreia Cathelin2, Didier Belot2, Pierre Vincent1 1 2 3 CEA-LET

Michael Q Gordon, Xiang Guan, Steve Lo, Patrick T McElwee, James Parker, Jon R Tani, Jeffery M Gilbert, Chinh H Doan SiBEAM, Sunnyvale, CA Recent advances in silicon technology, mm-Wave integrated circuit/antenna/package

multi-Gb/s wireless communication. Practical mm-Wave systems will require relatively large phased arrays in order to robustly overcome path-loss and fading issues. Despite significant progress [1,2], CMOS implementations

Modern high-speed wireless data links such as 60GHz RF and point-to-point communications activate research on Gb/s transceivers for V-band (50 to 75GHz) and W-band (75 to 110GHz). Conventional approaches in SiGe or III-V

William W. Si1, Burcin Baytekin1, Abbas Komijani1, Richard Chang1, Babak Vakili-Amini2, MeeLan Lee1, Haitao Gan1, Yashar Rajavi1, Hirad Samavati1, Brian Kaczynski1, Sang-Min Lee1, Sotirios Limotyrakis1, Hyunsik Park1, Ph

receiver front-end (RFE) for mobile TV covering the VHF-III (174 to 248MHz), UHF (470 to 862MHz) and L (1.4 to 1.7GHz) bands. The RFE (Fig. 9.7.1) is tailored to avert any external balun, or dedicated narrow-band radios,

area reduction in the analog/RF part is inevitable. While all-digital polar transmitters achieving a small die size are attracting attention and their application to Bluetooth Basic Rate and GSM standards is now the real

KAIST, Daejeon, Korea, ETRI, Daejeon, Korea One of the recent trends in multimode multiband (MMMB) receivers is to remove the analog filter or variable-gain amplifier (VGA) in the receiver chain and employ a wide-dynamic