2012

Bucknell Webb2, Lubomyr Romankiw2, Michele Petracca1, Ryan Davies1, Robert Fontana3, Gary Decad3, Ioannis Kymissis1, Angel Peterchev4, Luca Carloni1, William Gallagher2, Kenneth Shepard1 1 3 Columbia University, New York

applications such as smart buildings, medical implants, and surveillance systems. However, existing devices are bulky, measuring >1cm3, and they are hampered by short lifetimes and fail to realize the “smart dust” vision

Field-Effect Transistors)

area, delay, and power consumption of FPGAs relative to ASICs. In [1] it is estimated that a 3D-FPGA with the configuration memory stacked on top of the FPGA logic and routing can achieve 57% smaller die area than a base

Ramesh Singh1, Hesam Aslanzadeh1, Alireza Khalili1, Saurabh Vats1, Susan Arno1, Sean Campeau2 Applied Micro, Sunnyvale, CA Applied Micro, Kanata, ON, Canada 1 2 The IEEE802.3an 10GBase-T standard [1] provides full duplex

David Nguyen, Hiok-Tiaq Ng, Ramin Shirani Aquantia, Milpitas, CA High-density 48-port network switches demand very power-efficient, small form-factor quad PHYs which comply with the IEEE 802.3an transmit PSD and return-l

A burst-mode laser diode driver circuit (BLDD) for 10Gb/s-class passive optical network (10G-EPON) systems reduces power consumption by 94% while the laser diode (LD) is in the off state. The off-state optical launch pow

France 1 2 Emerging symmetric 10Gb/s passive optical network (PON) systems aim at high network transmission efficiency by reducing the RX settling time that is needed for RX amplitude recovery in burst-mode (BM). A conve

Future high-performance computing systems require sub-2pJ/bit power efficiencies at >10Gb/s [1-2]. The best reported optical link efficiencies at these data rates are ≥2.5pJ/bit [1-4]. This paper describes two VCSEL-base

T. Shimizu1, T. Sugimoto1, T. Kobayashi1, K. Inuzuka1, N. Kanagawa1, Y. Kajitani1, T. Ogawa1, J. Nakai1, K. Iwasa1, M. Kojima1, T. Suzuki1, Y. Suzuki1, S. Sakai1, T. Fujimura1, Y. Utsunomiya1, T. Hashimoto1, M. Miakashi1

This paper presents solid-state drives (SSDs) with two high reliability techniques. First, an error-prediction (EP) low-density-parity-check (LDPC) errorcorrecting code (ECC) that realizes an over 10× extended lifetime.

Solid-state drives (SSDs), built with many flash memory channels, is usually connected to the host through an advanced high-speed serial interface such as SATA III associated with a transfer rate of 6Gb/s [1-2]. However,

Christian Peters1, Christoph Parzinger1, Christoph Roll1, Stephan Kassenetter1, Stefanie Thierold1, Doris Schmitt-Landsiedel2 Infineon, Neubiberg, Germany, 2Technical University Munich, Munich, Germany 1 The markets tren

Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, Byung-Jun Min, Sung-Won Yun, Ji-Sang Lee, Il-Han Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yong-Sung Cho, Kyung-Min Kang, Sang

Yoshikazu Katoh1, Kouhei Tanabe2, Toshihiro Nakamura2, Yoshihiko Sumimoto2, Naoki Yamada2, Nobuyuki Nakai2, Shoji Sakamoto2, Yukio Hayakawa1, Kiyotaka Tsuji1, Shinichi Yoneda1, Atsushi Himeno1, Ken-ichi Origasa2, Kazuhik

mobile chips, such as energy-harvestingpowered devices and biomedical applications, require low-VDD on-chip nonvolatile memory (NVM) for low-power active-mode access and power-off data storage. However, conventional NVMs

Nima Mokhlesi1, Cynthia Hsu1, Jason Li1, Venky Ramachandra1, Teruhiko Kamei1, Masaaki Higashitani1, Tuan Pham1, Mitsuaki Honma2, Yoshihisa Watanabe2, Kazumi Ino2, Binh Le1, Byungki Woo1, Khin Htoo1, Tai-Yuan Tseng1, Long

Yasunori Aoki1, Yusuke Shinohe1, Koki Uchino1, Yuhei Hashimoto1, Fumihiro Nishiyama1, Hiroaki Miyachi1, Ikuho Nagase2, Itaru Uezono2, Rie Hisamura2, Itaru Maekawa1 Sony, Tokyo, Japan Sony Semiconductor, Kagoshima, Japan

Short-distance (<10cm) wireless communications applications are rapidly expanding. For instance, a fast file transfer by “touch-and-proceed data communication” provides a user-friendly interface for electronic products [

Narrow-band phased-array transmitters provide an efficient way of obtaining higher power through spatial combining and achieving higher transmitter EIRP. They also provide beamforming and beam-steering capabilities [1].

PHYCHIPS, Daejeon, Korea 1 2 Wake-up radios have been a popular transceiver architecture in recent years for battery-powered applications such as wireless body area networks (WBANs) [1], wireless sensor networks (WSNs) [

3/2.4GHz multi-standard transmitter (TX) for wireless sensor networks and wireless body area networks. Several 2.3/2.4GHz wireless standards have been proposed for such applications, including IEEE802.15.6 (BAN) for body

Xiongchuan Huang1, Cui Zhou1, Mario Konijnenburg1, Kathleen Philips1, Harmke De Groot1 imec - Holst Centre, Eindhoven, The Netherlands NXP Semiconductors, Eindhoven, The Netherlands 1 2 Any around-the-body wireless syste

free-of-maintenance solution for wireless sensor network (WSN) applications. By combining sensing functionalities and batteryless (RFID-like) wireless connectivity, these devices provide a viable option for all those sce

Netherlands 1 2 Minimizing the power consumption while maintaining performance is paramount in radio transceiver design for low-power wireless sensor network (WSN) applications. Given a sub-mW power budget, many radios h

The growth in communications coupled with the move towards multi-carrier, multi-band, multi-standard radio transmitters have helped drive high-speed digital-to-analog converter (DAC) technology for over a decade. The cri

design of switched-capacitor amplification circuits, designers must consider a growing number of design tradeoffs and employ new circuit techniques in order to achieve required accuracies, often at a cost of added power

The opamps in a switched-capacitor (SC) pipelined ADC provide the functions of sample-and-hold, residue generation, and residue amplification [1,2]. High-performance opamps that meet the requirements for dc gain, speed,

Time-to-digital converters (TDCs) were historically used in laser range-finding, automatic test equipment, and timing jitter measurements, but recent developments in the design of high-resolution TDCs have paved the way

Renesas Electronics, Kawasaki, Japan 1 2 In recent years ADC research has resulted in impressive advances in power efficiency. SAR ADCs have reached energies per conversion step below 10fJ, but only at rather low samplin

In recent years, charge-redistribution SAR (Successive Approximation) ADCs have exhibited the highest conversion efficiencies for ADCs with moderate resolution and bandwidth [1-3]. For effective resolutions beyond 10b or

to develop more innovative systems to improve performance. Remarkable improvements have been recently realized on charge-domain SAR ADCs to reach the speed of a few tens of MS/s with medium resolution and low power consu

However, each application has different requirements for accuracy and bandwidth. Recent power-efficient ADCs for sensor applications are mostly designed for a fixed accuracy and a limited range of sample rates [1,2]. An

National Semiconductor, Santa Clara, CA which may be done simply by changing the gain combination in the two cascaded gain stages. Such optimization may lead to further reduction in power consumption and also allow for l

building blocks of on-die interconnect fabrics that are critical to overall throughput and energy efficiency of high performance systems [1,2]. Conventional routers use distinct logic blocks for routing data and handling

Unlike human brains, where various kinds of visual recognition tasks are carried out with homogeneous neocortical circuits and a unified working mechanism, existing visual recognition processors [1-4] rely on multiple al

University of Siena, Siena, Italy 3 University of Michigan, Ann Arbor, MI 4 University of California at Berkeley, Berkeley, CA 1 2 Flip-flops (FFs) are key building blocks in the design of high-speed energy-efficient mic

digital systems with limited energy budget (e.g. mobile, battery-powered devices, radio frequency identification (RFID), wireless sensor networks, or biomedical applications). Subthreshold operation allows for such low p

Scaling power supply voltages (VDD’s) of logic circuits down to the sub/nearthreshold region is a promising approach to achieve significant power reductions. Circuit delays in the ultra-low voltage region, however, are e

and correcting transient delay errors have been proposed [1-5]. These Razor-style systems replace critical flip-flops with ones that detect late arriving signals, and use architectural replay to correct errors. However,

François Durvaux1, Sarah Boyd2, Denis Flandre1, Jean-Didier Legat1 1 2 Université catholique de Louvain, Louvain-la-Neuve, Belgium P.E. International, Berkeley, CA The vision of the Internet of Things with ambient intell

exhibits improved energy efficiency compared to nominal super-threshold operation [1, 2]. Two critical bottlenecks prevent mainstream adoption of low-VDD operation: degraded logic delay resulting in significantly lower t

processor codenamed Ivy Bridge that integrates up to four high-performance Intel Architecture (IA) cores, a power/performance optimized graphics/media processing unit (GPU), as well as memory, PCIe, and display controlle

Brian Miller, Derek Brasili, Tim Kiszely, Rob Kuhn, Rahul Mehrotra, Manan Salvi, Mandar Kulkarni, Anand Varadharajan, Shi-Huang Yin, William Lin, Adam Hughes, Bill Stysiack, Vasu Kandadi, Ilan Pragaspathi, Dan Hartman, D

Youngmoon Choi, Harikaran Sathianathan, Sudesna Dash, Sebastian Turullols, Song Kim, Robert Masleid, Georgios Konstadinidis, Robert Golla, Mary Jo Doherty, Greg Grohoski, Curtis McAllister Oracle, Santa Clara, CA The T4

Rahul Limaye3, Jon Duster1, Yulin Tan1, Ajay Balankutty1, Erkan Alpman1, Chun Lee1, Satoshi Suzuki1, Brent Carlton1, Hyung Seok Kim1, Marian Verhelst1, Stefano Pellerano1, Tong Kim2, Durgesh Srivastava1, Satish Venkatesa

simple programming model. Recently, however, the message-passing mechanism is also drawing attention due to its potentially better scalability [1-2]. In this work, we demonstrate that a hybrid communication mechanism sup

Praveen Salihundam1, Shiva Ramani1, Sriram Muthukumar1, Srinivasan M1, Arun Kumar1, Shasi Kumar Gb1, Rajaraman Ramanarayanan1, Vasantha Erraguntla1, Jason Howard2, Sriram Vangal2, Saurabh Dighe2, Greg Ruhl2, Paolo Aseron

Ann Arbor, MI 1 2 AMD’s 4+ GHz x86-64 core codenamed “Piledriver” employs resonant clocking [1-4] to reduce clock distribution power up to 24% while maintaining a low clock-skew target. To support testability and robust

including CPU, graphics, I/O interface, wireless transceivers and the power management unit, operate at different frequencies as shown in Fig. 3.8.1. In addition, maximizing battery life requires localized dynamic voltag