ISSCC 2013

2013

210 篇论文 · Wireless (34) · Memory (26) · Digital Circuits (17) · Medical & Bio (17) · Wireline I/O (17)

ISSCC 2013 Session 8 mm-Wave
A Low-Cost Miniature 120GHz SiP FMCW/CW Radar Sensor with Software Linearization
Yaoming Sun1, Miroslav Marinkovic1, Gunter Fischer1, Wolfgang Winkler2,
Wojceich Debski2, Stefan Beer3, Thomas Zwick3, Mekdes G. Girma4, Juergen Hasch4, Christoph J. Scheytt5 IHP, Frankfurt Oder, Germany, Silicon Radar, Frankfurt Oder, Germany, 3 Karlsruhe Institute of Technology, Karlsruhe,
ISSCC 2013 Session 8 mm-Wave
A 10mW 37.8GHz Current-Redistribution BiCMOS VCO with an Average FOMT of -193.5dBc/Hz
Qiyang Wu1, Tony Quach2, Aji Mattamana2, Salma Elabd1,
Steven R. Dooley2, Jamin J McCue1, Pompei L. Orlando2, Gregory L. Creech2, Waleed Khalil1 Ohio State University, Columbus, OH, Air Force Research Laboratory, Wright-Patterson AFB, Dayton, OH 1 Figure 8.8.3 shows the sche
ISSCC 2013 Session 9 Digital Processors
28nm High-κ Metal-Gate Heterogeneous Quad-Core CPUs for High-Performance and Energy-Efficient Mobile Application Processor
Youngmin Shin1, Ken Shin1, Prashant Kenkare2, Rajesh Kashyap2,
Hoi-Jin Lee1, Dongjoo Seo1, Brian Millar2, Yohan Kwon1, Ravi Iyengar2, Min-Su Kim1, Ahsan Chowdhury2, Sung-Il Bae1, Inpyo Hong1, Wookyeong Jeong2, Aaron Lindner2, Ukrae Cho1, Keith Hawkins2, Jae Cheol Son1, Seung Ho Hwan
ISSCC 2013 Session 9 Digital Processors
A 28nm High-κ Metal-Gate Single-Chip Communications Processor with 1.5GHz Dual-Core Application Processor and LTE/HSPA+-Capable Baseband Processor
Masaki Fujigaya1, Noriaki Sakamoto1, Takao Koike1, Takahiro Irita1,
Kohei Wakahara1, Tsugio Matsuyama1, Keiji Hasegawa1, Toshiharu Saito1, Akira Fukuda1, Kaname Teranishi1, Kazuki Fukuoka2, Noriaki Maeda2, Koji Nii2, Takeshi Kataoka1, Toshihiro Hattori1 Renesas Mobile, Tokyo, Japan, Rene
ISSCC 2013 Session 9 Digital Processors
A 0.48V 0.57nJ/Pixel Video-Recording SoC in 65nm CMOS
Tay-Jyi Lin1, Cheng-An Chien1, Pei-Yao Chang1, Ching-Wen Chen2,
Po-Hao Wang3, Ting-Yu Shyu1, Chien-Yung Chou2, Shien-Chun Luo2, Jiun-In Guo3, Tien-Fu Chen3, Gene C.H. Chuang2, Yuan-Hua Chu2, Liang-Chia Cheng2, Hong-Men Su4, Chewnpu Jou5, Meikei Ieong5, Cheng-Wen Wu2, Jinn-Shyan Wang1
ISSCC 2013 Session 9 Digital Processors
GFLOPS 240Mpixel/s 1080p 60fps Multi-Format Video Codec Application Processor Enabled with GPGPU for Fused Multimedia Application
Yongha Park, Changhyo Yu, Kilwhan Lee, Hyunsuk Kim,
Youngeun Park, Chunho Kim, Yunseok Choi, Jinhong Oh, Changhoon Oh, Gurnrack Moon, Sangduk Kim, Horang Jang, Jin-Aeon Lee, Chinhyun Kim, Sungho Park Samsung Electronics, Yongin, Korea 72.5GFLOPS GPGPU computing, 240 Mpixe
ISSCC 2013 Session 9 Digital Processors
A 249Mpixel/s HEVC Video-Decoder Chip for Quad Full HD Applications
Chao-Tsung Huang1, Mehul Tikekar1, Chiraag Juvekar1, Vivienne Sze2, Anantha Chandrakasan1
(HEVC) [1] provides 50% improvement in coding efficiency compared to H.264/AVC, to meet the rising demand for video streaming, better video quality and higher resolutions. The coding gain is achieved using more complex t
Massachusetts Institute of Technology, Cambridge, MA, Texas Instrument
ISSCC 2013 Session 9 Digital Processors
Reconfigurable Processor for Energy-Scalable Computational Photography
Rahul Rithe1, Priyanka Raina1, Nathan Ickes1, Srikanth V. Tenneti2, Anantha P. Chandrakasan1
photography [1], enable capture and synthesis of images that could not be captured with a traditional camera. Non-linear filtering techniques like bilateral filtering [2] form a significant part of computational photogra
Massachusetts Institute of Technology, Cambridge, MA, California Insti
ISSCC 2013 Session 9 Digital Processors
A 470mV 2.7mW Feature Extraction-Accelerator for Micro-Autonomous Vehicle Navigation in 28nm CMOS
Dongsuk Jeon, Yejoong Kim, Inhee Lee, Zhengya Zhang, David Blaauw, Dennis Sylvester
University of Michigan, Ann Arbor, MI Recently, computer vision technologies are being applied to smaller systems such as cell phones, digital cameras, and unmanned surveillance platforms [1]. Feature extraction is a cri
ISSCC 2013 Session 9 Digital Processors
A 646GOPS/W Multi-Classifier Many-Core Processor with Cortex-Like Architecture for Super-Resolution Recognition
Junyoung Park, Injoon Hong, Gyeonghoon Kim, Youchang Kim,
autonomic vehicle navigation, smart surveillance and unmanned air vehicles (UAVs) [1-3]. Most of the processors adopt a single classifier rather than multiple classifiers even though multi-classifier systems (MCSs) offer
Kyuho Lee, Seongwook Park, Kyeongryeol Bong, Hoi-Jun Yoo KAIST, Daejeo