ISSCC 2014
Session 3
RF & Wireless
An RF-to-BB Current-Reuse Wideband Receiver with Parallel N-Path Active/Passive Mixers and a Single-MOS Pole-Zero LPF
UMTEC, Macao, China, 3 Instituto Superior Tecnico, Lisbon, Portugal 1 2 The latest passive-mixer-first wideband receiver (RX) [1] has managed to squeeze the power (10 to 12mW) via resonant multi-phase LO and current-reus
ISSCC 2014
Session 30
Other
8b Thin-Film Microprocessor Using a Hybrid OxideOrganic Complementary Technology with InkjetPrinted P2ROM Memory
Tung Huei Ke1, Soeren Steudel1, Koji Obata3, Marko Marinkovic4, Duy-Vu Pham4, Arne Hoppe4, Aashini Gulati5, Francisco Gonzalez Rodriguez5, Brian Cobb5, Gerwin H. Gelinck5, Jan Genoe1,2, Wim Dehaene1,2, Paul Heremans1,2 i
ISSCC 2014
Session 30
Other
A 1TOPS/W Analog Deep Machine-Learning Engine with Floating-Gate Storage in 0.13µm CMOS
Direct processing of raw high-dimensional data such as images and video by machine learning systems is impractical both due to prohibitive power consumption and the “curse of dimensionality,” which makes learning tasks e
ISSCC 2014
Session 30
Other
Digital PWM-Driven AMOLED Display on Flex Reducing Static Power Consumption
Manoj Nag1, Soeren Steudel1, Sarah Schols1, Joris Maas4, Ashutosh Tripathi4, Jan-Laurens van der Steen4, Tim Ellis4, Gerwin H. Gelinck4, Paul Heremans1,2,4 imec, Leuven, Belgium, 2KU Leuven, Leuven, Belgium, Panasonic, O
ISSCC 2014
Session 30
Other
Organic-Transistor-Based 2kV ESD-Tolerant Flexible Wet Sensor Sheet for Biomedical Applications with Wireless Power and Data Transmission Using 13.56MHz Magnetic Resonance
the reference RC oscillator 1 is 10Hz, RC oscillator 2 (= Sensor 1) is not oscillating, which corresponds to “Dry” (= no urination), and RC oscillator 3 (= Sensor 2) is 5Hz, which corresponds to “Wet” (= urination). Figu
ISSCC 2014
Session 30
Other
A 13.56MHz RFID Tag with Active Envelope Detection in an Organic Complementary TFT Technology
University of Technology, Eindhoven, The Netherlands, 4 CEA-LITEN, Grenoble, France 1 3 In the last several years, organic electronics have gained increasing consideration as a cost-effective alternative to silicon, espe
ISSCC 2014
Session 30
Other
A GaN 3×3 Matrix Converter Chipset with Drive-by-Microwave Technologies
power and frequency by bidirectional switches has been expected to be an ultimate AC-to-AC converter because it eliminates limited-lifetime capacitors and achieves high efficiency power conversion even without PFC (Power
ISSCC 2014
Session 30
Other
An Electromagnetic Clip Connector for In-Vehicle LAN to Reduce Wire Harness Weight by 30%
Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda and negative pulses are received for each bit due to Manchester encoding, error propagation can be limited within two bits. Therefore, FEC techniques can be applied. If the
ISSCC 2014
Session 30
Other
A 60Mb/s Wideband BCC Transceiver with 150pJ/b RX and 31pJ/b TX for Emerging Wearable Applications
Jia Hao Cheong1, Peng Li1, Jun Zhou1, Wei Da Toh1, Xin Zhang1, Yuan Gao1, Kuang Wei Cheng2, Xin Liu1, Minkyu Je1 Institute of Microelectronics, Singapore, Singapore, National Cheng Kung University, Tainan, Taiwan 1 2 Wea
ISSCC 2014
Session 30
Other
A 30GS/s Double-Switching Track-and-Hold Amplifier with 19dBm IIP3 in an InP BiCMOS Technology
Thomas C. Oh4, James F. Buckwalter2 Qualcomm, San Diego, CA, University of California, San Diego, La Jolla, CA, 3 Peregrine Semiconductor, San Diego, CA, 4 HRL Laboratories, Malibu, CA 1 2 High-speed track-and-hold ampli
ISSCC 2014
Session 30
Other
Normally-Off Computing with Crystalline InGaZnO-based FPGA
Munehiro Kozuma1, Takeshi Osada1, Yoshiyuki Kurokawa1, Takayuki Ikeda1, Naoto Yamade1, Yutaka Okazaki1, Hidekazu Miyairi1, Masahiro Fujita2, Jun Koyama1, Shunpei Yamazaki1 Semiconductor Energy Laboratory, Kanagawa, Japan
ISSCC 2014
Session 4
Power Management
A 3-Phase Digitally Controlled DC-DC Converter with 88% Ripple Reduced 1-Cycle Phase Adding/Dropping Scheme and 28% Power Saving CT/DT Hybrid Current Control
wide range of load current, especially for today’s multicore SoCs, which usually have a wide range of current profile. Active-phase-count (APC) control, as proposed in [1-3], is the key technique that offers the wide loa
ISSCC 2014
Session 4
Power Management
A 6A 40MHz Four-Phase ZDS Hysteretic DC-DC Converter with 118mV Droop and 230ns Response Time for a 5A/5ns Load Transient
In recent years, the clock frequency, the number of cores, and the power dissipation of application processors (APs) for portable electronics have dramatically increased. As a result, peak processor currents have reached
ISSCC 2014
Session 4
Power Management
An 87%-Peak-Efficiency DVS-Capable SingleInductor 4-Output DC-DC Buck Converter with Ripple-Based Adaptive Off-Time Control
Improving battery longevity in portable devices usually requires the use of different voltage levels with a wide range of load capability for various functional blocks. Since a single-inductor-multiple-output (SIMO) conv
ISSCC 2014
Session 4
Power Management
A 10/30MHz Wide-Duty-Cycle-Range Buck Converter with DDA-Based Type-III Compensator and Fast Reference-Tracking Responses for DVS Applications
Dynamic voltage scaling (DVS) is an effective strategy in reducing the power consumption of a processor through adjusting its supply voltage at runtime. The power converter that drives the processor should have a wide ou
ISSCC 2014
Session 4
Power Management
A 2-Phase Resonant Switched-Capacitor Converter Delivering 4.3W at 0.6W/mm2 with 85% Efficiency
There is an increasing need for fully integrated power converters to reduce form factor in mobile devices and provide high-density point-of-load power delivery in performance computing applications [1]. While the number
ISSCC 2014
Session 4
Power Management
An 85%-Efficiency Fully Integrated 15-Ratio Recursive Switched-Capacitor DC-DC Converter with 0.1-to-2.2V Output Voltage Range
The growing demand for both performance and battery life in portable consumer electronics requires SoCs and power management circuits to be small, efficient, and dynamically powerful. Dynamic voltage scaling (DVS) can he
ISSCC 2014
Session 4
Power Management
A Sub-ns Response On-Chip Switched-Capacitor DC-DC Voltage Regulator Delivering 3.7W/mm2 at 90% Efficiency Using Deep-Trench Capacitors in 32nm SOI CMOS
Thomas Toifl2, Christian Menolfi2, Lukas Kull2, Thomas Morf2, Marcel Kossel2, Matthias Brändli2, Peter Buchmann2, Pier Andrea Francese2 ETH, Zurich, Switzerland, 2IBM Research, Rüschlikon, Switzerland 1 For an on-chip or
ISSCC 2014
Session 4
Power Management
3-Phase 6/1 Switched-Capacitor DC-DC Boost Converter Providing 16V at 7mA and 70.3% Efficiency in 1.1mm3
In this paper, a 3-phase switched-capacitor (SC) boost converter that uses 2 external floating capacitors to provide 16V output from a 3.3V input is presented. It achieves an efficiency of 70.3% at 7mA load current while
ISSCC 2014
Session 5
Digital Processors
POWER8TM: A 12-Core Server-Class Processor in 22nm SOI with 7.6Tb/s Off-Chip Bandwidth
Gregory Still3, Christopher Gonzalez2, Allen Hall1, David Hogenmiller1, Frank Malgioglio4, Ryan Nett1, Jose Paredes1, Juergen Pille5, Donald Plass4, Ruchir Puri2, Phillip Restle2, David Shan1, Kevin Stawiasz2, Zeynep Top
ISSCC 2014
Session 5
Digital Processors
Distributed System of Digitally Controlled Microregulators Enabling Per-Core DVFS for the POWER8TM Microprocessor
Gregory Still3, Ryan Kruse4, Seongwon Kim1, David Boerstler4, Tilman Gloekler5, Raphael Robertazzi1, Kevin Stawiasz1, Timothy Diemoz2, George English2, David Hui2, Paul Muench2, Joshua Friedrich4 IBM, Yorktown Heights, N
ISSCC 2014
Session 5
Digital Processors
Wide-Frequency-Range Resonant Clock with On-the-Fly Mode Changing for the POWER8TM Microprocessor
4IBM STG, Williston, VT, 5IBM STG, Raleigh, NC 1 3 A resonant-clock design for the IBM POWER8 processor core was implemented with 2 resonant modes (and a non-resonant mode), saving clock power over a wide frequency range
ISSCC 2014
Session 5
Digital Processors
Ivytown: A 22nm 15-Core Enterprise Xeon® Processor Family
dual-threaded 64b Ivybridge cores [1] and 37.5MB shared L3 cache. The system interface includes two on-chip memory controllers, each with two memory channels and supports multiple system topologies. The processor has 4.3
ISSCC 2014
Session 5
Digital Processors
Steamroller: An x86-64 Core Implemented in 28nm Bulk CMOS
Stephen Kosonocky2, Robert S. Orefice1, Donald A. Priore1, Jonathan White1, Kathryn Wilcox1 AMD, Boxborough, MA, 2AMD, Fort Collins, CO, 3AMD, Austin, TX 1 The AMD two-core x86-64 CPU module, codenamed “Steamroller”, con
ISSCC 2014
Session 5
Digital Processors
Adaptive Clocking System for Improved Power Efficiency in a 28nm x86-64 Microprocessor
In high-performance microprocessor cores, the on-die supply voltage seen by the transistors is non-ideal and exhibits significant fluctuations. These supply fluctuations are caused by sudden changes in the current consum
ISSCC 2014
Session 5
Digital Processors
A Graphics Execution Core in 22nm CMOS
Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De Intel, Hillsboro, OR
ISSCC 2014
Session 5
Digital Processors
A 3GHz 64b ARM v8 Processor in 40nm Bulk CMOS Technology
John Ngai, Russ Homer, Matthew Ashcraft, Greg Favor Applied Micro, Sunnyvale, CA Potenza is a first generation 64b ARM v8 processor and memory sub-system of the X-GeneTM server platform [1]. The Potenza processor module
ISSCC 2014
Session 5
Digital Processors
Haswell: A Family of IA 22nm Processors
Thomas P. Thomas, Christopher Mozak, Brent Boswell, Manoj Lal, Anant Deval, Jonathan Douglas, Mahmoud Elassal, Ankireddy Nalamalpu, Timothy M. Wilson, Matthew Merten, Srinivas Chennupaty, Wilfred Gomes, Rajesh Kumar Inte
ISSCC 2014
Session 6
Other
Memory and System Architecture for 400Gb/s Networking and Beyond Dinesh Maheshwari
and limited by the Random Transaction Rate (RTR) of the memory system. Networking line cards to date are ≤200Gb/s and were able to use memories optimized for latency (SRAM) and bandwidth (SDRAM) designed for computing sy
ISSCC 2014
Session 6
Other
High-Capacity Scalable Optical Communication for Future Optical Transport Network
The future penetration of long-term-evolution mobile phone services and various data cloud services will continuously accelerate the present traffic evolution. Figure 6.2.1 shows the commercial system capacity evolution
ISSCC 2014
Session 6
Other
A Heterogeneous 3D-IC Consisting of Two 28nm FPGA Die and 32 Reconfigurable High-Performance Data Converters
Aidan Keady1, John McGrath1, Edward Cullen1, Daire Breathnach1, Denis Keane1, Patrick Lynch1, Marites De La Torre1, Ronnie De La Torre1, Peng Lim1, Anthony Collins1, Brendan Farley1, Liam Madden2 Xilinx, Dublin, Ireland,
ISSCC 2014
Session 7
Image Sensors
A 1/4-inch 8Mpixel CMOS Image Sensor with 3D Backside-Illuminated 1.12µm Pixel with Front-Side Deep-Trench Isolation and Vertical Transfer Gate
Bumsuk Kim, Hongki Kim, Jongeun Park, Taesub Jung, Wonje Park, Taeheon Lee, Eunkyung Park, Sangjun Choi, Gyehun Choi, Haeyong Park, Yujung Choi, Seungwook Lee, Yunkyung Kim, Y. Jay Jung, Donghyuk Park, Seungjoo Nah, Youn
ISSCC 2014
Session 7
Image Sensors
pJ/pixel Bio-Inspired Time-Stamp-Based 2D Optic Flow Sensor for Artificial Compound Eyes
Miniaturized low-power artificial compound eyes in a small form factor and a low payload can be a promising approach to provide wide-field information for micro-air-vehicle (MAV) applications. Recently, research efforts
ISSCC 2014
Session 7
AI / ML
A 1000fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array and Self-Organizing Map Neural Network
that integrates an image sensor and parallel image processors on a single silicon die. Nowadays, high-speed vision chips with powerful recognition capabilities are greatly demanded in applications such as: industrial aut
ISSCC 2014
Session 7
Image Sensors
A 413×240-Pixel Sub-Centimeter Resolution Time-of-Flight CMOS Image Sensor with In-Pixel Background Canceling Using Lateral-Electric-Field Charge Modulators
have a wide range of applications, such as 3D mice, gesture-based remote controllers, amusement, robots, security systems, and automobiles. Numerous ToF range imager developments have been reported [1-4]. Recent developm
ISSCC 2014
Session 7
Image Sensors
A 0.3mm-Resolution Time-of-Flight CMOS Range Imager with Column-Gating Clock-Skew Calibration
combination with 3D printers. One of the common technologies in contactless 3D scanners is the light-section method, which has advantages in term of accuracy. The method, however, requires a long base line between a came
ISSCC 2014
Session 7
Image Sensors
A 512×424 CMOS 3D Time-of-Flight Image Sensor with Multi-Frequency Photo-Demodulation up to 130MHz and 2GS/s ADC
Cyrus S. Bamji, Dane Snow, Hideaki Oshima, Larry Prather, Mike Fenton, Lou Kordus, Pat O’Connor, Rich McCauley, Sheethal Nayak, Sunil Acharya, Swati Mehta, Tamer Elkhatib, Thomas Meyer, Tod O’Dwyer, Travis Perry, Vei-Han
ISSCC 2014
Session 8
Wireline I/O
A 6Gb/s Transceiver with a Nonlinear Electronic Dispersion Compensator for Directly Modulated Distributed-Feedback Lasers
medium-reach optical links due to its cost effectiveness. However, DMLs are not appropriate for use in fiber links longer than 20km at 6Gb/s or equivalent, because the SNR penalty increases abruptly due to excessive chro
ISSCC 2014
Session 8
Wireline I/O
A 12×5 Two-Dimensional Optical I/O Array for 600Gb/s Chip-to-Chip Interconnect in 65nm CMOS
The aggregate bandwidth required between two processors, for example, is expected to extend into the terabit-per-second range or higher [1]. Bandwidth is typically the bottleneck in such situations. Optical interconnect
ISSCC 2014
Session 8
Wireline I/O
A Power-Scalable 7-Tap FIR Equalizer with Tunable Active Delay Line for 10-to-25Gb/s Multi-Mode Fiber EDC in 28nm LP-CMOS
cost-effective fiber for high-speed LANs. Modal dispersion leads to optical-energy spreading over several symbol periods, drastically limiting distance and data-rate. Compared with copper channels, equalization is challe
ISSCC 2014
Session 8
Wireline I/O
A 28Gb/s 1pJ/b Shared-Inductor Optical Receiver with 56% Chip-Area Reduction in 28nm CMOS
high-performance computing systems require high-bandwidth serial links to transport high-speed data streams among computational blocks. Optical links have recently attracted attention due to their low channel loss at hig
ISSCC 2014
Session 8
Wireline I/O
A Sub-1.75W Full-Duplex 10GBASE-T Transceiver in 40nm CMOS
Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M.L. van der Goes, Klaas Bult Broadcom, Bunnik, The Netherlands The IEEE802.3an 10GBASE-T standard describes full-duplex 10Gb/s Ethernet transmission over four
ISSCC 2014
Session 8
Wireline I/O
A Full-Duplex Line Driver for Gigabit Ethernet with Rail-to-Rail Class-AB Output Stage in 28nm CMOS
standalone PHY chips with hundreds of millions of ports shipped every year. Transceiver design has recently focused on power reduction driven by the need for higher port density and throughput with minimum energy and the
ISSCC 2014
Session 8
Wireline I/O
An 8.2-to-10.3Gb/s Full-Rate Linear Reference-less CDR Without Frequency Detector in 0.18µm CMOS
Broadcom, Irvine, CA 1 2 As an alternative to the conventional dual-loop architecture, reference-less CDR architectures have become more popular in industry because of their simplicity and flexibility [1-5]. However, the
ISSCC 2014
Session 8
Wireline I/O
A 40Gb/s VCSEL Over-Driving IC with Group-DelayTunable Pre-Emphasis for Optical Interconnection
high-performance computing systems and data centers are currently being developed. The transmission range of conventional electrical interconnections is limited due to the bandwidth of electrical channels. VCSEL-based op
ISSCC 2014
Session 9
Wireless
A Self-Calibrating NFC SoC with a Triple-Mode Reconfigurable PLL and a Single-Path PICC-PCD Receiver in 0.11µm CMOS
Eng Chuan Low1, Dan Ping Li1, Liming Jin1, Huajiang Zhang1, Chin Heng Leow1, Soong Lin Chew1, Uday Dasgupta1, Chee Hong Yong1, Tian Bao Gao1, Geok Teng Ong1, Wee Guan Tan1, Weimin Shu1, Chee Lee Heng1, Osama Shana’A1,2 M
ISSCC 2014
Session 9
Wireless
A 13.3mW 500Mb/s IR-UWB Transceiver with LinkMargin Enhancement Technique for Meter-Range Communications
medical equipment has not been rapidly developed. For wireless medical applications, lossless connection and noninvasive transmission are important factors. Moreover, in medical imaging applications such as 4D ultrasound
ISSCC 2014
Session 9
Wireless
A 1mW 1Mb/s 7.75-to-8.25GHz Chirp-UWB Transceiver with Low Peak-Power Transmission and Fast Synchronization Capability
constraints on the wireless links where the ear-to-ear link enables signal processing of sound for both ears to enhance speech intelligence and the ear-to-device link provides an audio channel to commercial electronics s
ISSCC 2014
Session 9
Wireless
A 0.5V 1.15mW 0.2mm2 Sub-GHz ZigBee Receiver Supporting 433/860/915/960MHz ISM Bands with Zero External Components
UMTEC, Macao, China, 3 Instituto Superior Tecnico, Lisbon, Portugal 1 2 The rapid proliferation of Internet of Things has urged the development of ultralow-power (ULP) radios at the lowest possible cost, while being univ
ISSCC 2014
Session 9
Wireless
A 1.2nJ/b 2.4GHz Receiver with a Sliding-IF Phaseto-Digital Converter for Wireless Personal/Body-Area Networks
4GHz RX for short-range wireless personal and body-area networks. In such applications, the RF transceiver consumes up to 90% of the total battery energy in a remote sensor node. In order to extend the operation lifetime