ISSCC 2014

2014

203 篇论文 · Digital Processors (19) · Wireless (19) · Data Converters (17) · Wireline I/O (17)

ISSCC 2014 Session 21 Clocking & PLLs
A Pulling Mitigation Technique for Direct-Conversion Transmitters
Ahmad Mirzaei, Mohyee Mikhemar, Hooman Darabi
Despite versatility and low power consumption, direct-conversion transmitters suffer from a fundamental drawback: the local oscillator disturbance by the power amplifier, through unwanted electromagnetic or capacitive co
Broadcom, Irvine, CA
ISSCC 2014 Session 22 Data Converters
A 90GS/s 8b 667mW 64× Interleaved SAR ADC in 32nm Digital SOI CMOS
Lukas Kull1,2, Thomas Toifl1, Martin Schmatz1, Pier Andrea Francese1,
Christian Menolfi1, Matthias Braendli1, Marcel Kossel1, Thomas Morf1, Toke Meyer Andersen1, Yusuf Leblebici2 IBM Research, Rüschlikon, Switzerland, EPFL, Lausanne, Switzerland 1 2 Forthcoming optical communication standa
ISSCC 2014 Session 22 Data Converters
A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI
Vanessa Hung-Chu Chen, Lawrence Pileggi
Low-power time-interleaved ADCs with high sampling rates of over 10GS/s are in high demand for wireline communication systems. However, the timeinterleaved channels suffer from process mismatch, particularly for timing s
Carnegie Mellon University, Pittsburgh, PA
ISSCC 2014 Session 22 Data Converters
A 20GHz-BW 6b 10GS/s 32mW Time-Interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI Technology
Stéphane Le Tual1, Pratap Narayan Singh2, Christophe Curis3, Pierre Dautriche1
France 1 After quantization, each SAR stores its 6b word in 2 ping-pong 512-word RAMs running at 10GHz/8/2=625MHz. The total 8K words are finally read at low speed through a JTAG controller. The chip is fabricated in 28n
STMicroelectronics, Crolles, France, STMicroelectronics, Greater Noida
ISSCC 2014 Session 22 Data Converters
A 1GS/s 10b 18.9mW Time-Interleaved SAR ADC with Background Timing-Skew Calibration
Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee
SARs are one of the most energy-efficient ADC architectures for medium resolution and low-to-medium speed. To improve the limited bandwidth of SAR ADCs, the time-interleaved (TI) structure is often used [1,2]. However, T
Massachusetts Institute of Technology, Cambridge, MA
ISSCC 2014 Session 22 Data Converters
A 1.62GS/s Time-Interleaved SAR ADC with Digital Background Mismatch Calibration Achieving Interleaving Spurs Below 70dBFS
Nicolas Le Dortz1,2, Jean-Pierre Blanc1, Thierry Simon1,
Sarah Verhaeren1, Emmanuel Rouat1, Pascal Urard1, Stéphane Le Tual1, Dimitri Goguet1, Caroline Lelandais-Perrault2, Philippe Benabes2 STMicroelectronics, Crolles, France, Supélec, Gif-sur-Yvette, France 1 2 Today’s appli
ISSCC 2014 Session 22 Data Converters
A 2.2GS/s 7b 27.4mW Time-Based Folding-Flash ADC with Resistively Averaged Voltage-to-Time Amplifiers
Masaya Miyahara, Ibuki Mano, Masaaki Nakayama,
as 60GHz receivers, serial links, and high-density disk drive systems. Flash architectures have the highest conversion rate without employing time interleaving. Moreover, flash architectures have the lowest latency, whic
Kenichi Okada, Akira Matsuzawa Tokyo Institute of Technology, Tokyo, J
ISSCC 2014 Session 22 Data Converters
A 14b 4.6GS/s RF DAC in 0.18µm CMOS for Cable Head-End Systems
Brian Brandt1, Dan McMahill2, Miaochen Wu1,
Paul Kalthoff3, Ajay Kuckreja4, Geir Ostrem3 Maxim Integrated, North Chelmsford, MA, 2Maxim Integrated, Woodstock, GA, Maxim Integrated, Colorado Springs, CO, 4Maxim Integrated, Boulder, CO 1 the other input is driven to
ISSCC 2014 Session 23 Power Management
A 0.15V-Input Energy-Harvesting Charge Pump with Switching Body Biasing and Adaptive Dead-Time for Efficiency Improvement
Jungmoon Kim1,2, Philip K. T. Mok1, Chulwoo Kim2
Korea University, Seoul, Korea 1 2 Design of low-voltage and efficient energy-harvesting circuits is becoming increasingly important, particularly, for autonomous systems. Since the amount of energy that can be harvested
Hong Kong University of Science and Technology, Hong Kong, China
ISSCC 2014 Session 23 Power Management
A 1.1nW Energy Harvesting System with 544pW Quiescent Power for Next-Generation Implants
Saurav Bandyopadhyay1,*, Patrick P. Mercier1,2, Andrew C. Lysaght3,
Konstantina M. Stankovic3,4, Anantha P. Chandrakasan1 Massachusetts Institute of Technology, Cambridge, MA, University of California, San Diego, La Jolla, CA, 3 Massachusetts Eye and Ear Infirmary, Boston, MA, 4 Massachu
ISSCC 2014 Session 23 Power Management
A 3nW Fully Integrated Energy Harvester Based on Self-Oscillating Switched-Capacitor DC-DC Converter
Wanyeong Jung, Sechang Oh, Suyoung Bang, Yoonmyung Lee,
mm-scale wireless systems
Dennis Sylvester, David Blaauw University of Michigan, Ann Arbor, MI R
ISSCC 2014 Session 23 Power Management
Dual-Source Single-Inductor 0.18µm CMOS Charger-Supply with Nested Hysteretic and Adaptive On-Time PWM Control
Suhwan Kim, Gabriel A. Rincón-Mora, LO from vES to ground across τEN’s 1.2μs pulsewidth to raise LO’s current iL from
zero to 30mA. Afterwards, SES and SE open and SDE and SO close to drain LO into vO. SDE then opens and, if GHV senses that vO still needs power, vSAW starts ramping and SPE closes to energize LO from vPS to vO. When vSAW
ISSCC 2014 Session 23 Power Management
An Energy Pile-Up Resonance Circuit Extracting Maximum 422% Energy from Piezoelectric Material in a Dual-Source Energy-Harvesting Interface
Young-Sub Yuk, Seungchul Jung, Hui-Dong Gwon, Sukhwan Choi,
Si Duk Sung, Tae-Hwang Kong, Sung-Wan Hong, Jun-Han Choi, Min-Yong Jeong, Jong-Pil Im, Seung-Tak Ryu, Gyu-Hyeong Cho KAIST, Daejeon, Korea Energy harvesting is one of the key technologies used to realize self-sustaining
ISSCC 2014 Session 23 Power Management
A 43V 400mW-to-21W Global-Search-Based Photovoltaic Energy Harvester with 350µs
Transient Time, 99.9% MPPT Efficiency, and 94% Power Efficiency
and remote monitoring stations can be self-powered by solar panels (SPs) having output powers of tens of watts. When the size of the SP is large, part of it can be shaded by birds, trees and other objects resulting in pa
Sandip Uprety, Hoi Lee University of Texas, Dallas, Richardson, TX Sta
ISSCC 2014 Session 23 Power Management
Self-Powered 30µW-to-10mW Piezoelectric EnergyHarvesting System with 9.09ms/V Maximum Power Point Tracking Time
Minseob Shim, Jungmoon Kim, Junwon Jung, Chulwoo Kim
Energy harvesting is a key technology in various small-size applications such as wireless sensor nodes, mobile devices, and implantable bio-devices to improve battery lifetime or to substitute for batteries. Piezoelectri
Korea University, Seoul, Korea
ISSCC 2014 Session 23 Power Management
A 34V Charge Pump in 65nm Bulk CMOS Technology
Yousr Ismail1, Haechang Lee2,*, Sudhakar Pamarti1, Chih-Kong Ken Yang1
University of California, Los Angeles, CA, 2SiTime, Sunnyvale, CA now with Altera, San Jose, CA 1 * Recent advances in MEMS-based oscillators have resulted in their proliferation in timing applications that were once exc
ISSCC 2014 Session 24 Medical & Bio
A Miniaturized 64-Channel 225µW Wireless Electrocorticographic Neural Sensor
Rikky Muller1,2, Hanh-Phuc Le1, Wen Li1, Peter Ledochowitsch1,
Simone Gambini2, Toni Bjorninen3, Aaron Koralek1, Jose M. Carmena1, Michel M. Maharbiz1, Elad Alon1, Jan M. Rabaey1 University of California, Berkeley, CA, University of Melbourne, Parkville, Australia, 3 Tampere Univers
ISSCC 2014 Session 24 Medical & Bio
A Power-Efficient Switched-Capacitor Stimulating System for Electrical/Optical Deep-Brain Stimulation
Hyung-Min Lee1, Ki-Yong Kwon2, Wen Li2, Maysam Ghovanloo1
Michigan State University, East Lansing, MI 1 2 Deep-brain stimulation (DBS) has been proven as an effective therapy to alleviate Parkinson’s disease, tremor, and dystonia. Towards a less invasive headmounted DBS, we uti
Georgia Institute of Technology, Atlanta, GA,
ISSCC 2014 Session 24 Medical & Bio
An Implantable 64nW ECG-Monitoring Mixed-Signal SoC for Arrhythmia Diagnosis
Dongsuk Jeon1, Yen-Po Chen1, Yoonmyung Lee1, Yejoong Kim1,
Zhiyoong Foo1, Grant Kruger1, Hakan Oral2, Omer Berenfeld2, Zhengya Zhang1, David Blaauw1, Dennis Sylvester1 University of Michigan, Ann Arbor, MI, University of Michigan Health System, Ann Arbor, MI 1 2 Electrocardiogra
ISSCC 2014 Session 24 Medical & Bio
A 680nA Fully Integrated Implantable ECGAcquisition IC with Analog Feature Extraction
Long Yan1, Pieter Harpe2, Masato Osawa3, Yasunari Harada3,
Leuven, Belgium 1 2 Ultra-low power consumption and miniature size are by far the most important design requirements for implantable pacemakers. In order to guarantee a long life span of the device, saving power in the s
Kosei Tamiya3, Chris Van Hoof1,4, Refet Firat Yazicioglu1 imec, Heverl
ISSCC 2014 Session 24 Medical & Bio
A 0.5V 1.27mW Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia
Kea-Tiong Tang1, Shih-Wen Chiu1, Chung-Hung Shih2,
Chia-Ling Chang1, Chia-Min Yang1, Da-Jeng Yao1, Jen-Huo Wang1, Chien-Ming Huang1, Hsin Chen1, Kwuang-Han Chang1, Chih-Cheng Hsieh1, Ting-Hau Chang1, Meng-Fan Chang1, Chia-Min Wang1, Yi-Wen Liu1, Tsan-Jieh Chen3, Chia-Hsi
ISSCC 2014 Session 24 Medical & Bio
A CMOS Micro-Flow Cytometer for Magnetic Label Detection and Classification
Pramod Murali, Igor Izyumin, Daniel Cohen, Jun-Chau Chien,
Ali M. Niknejad, Bernhard Boser University of California, Berkeley, CA Flow cytometry is widely used in medicine for hematology, immunology, chemotherapy and pathology, as well as in food and water safety. While present
ISSCC 2014 Session 24 Medical & Bio
A 60nV/√Hz 15-Channel Digital Active Electrode System for Portable Biopotential Signal Acquisition
Jiawei Xu1,2, Benjamin Busze1, Hyejung Kim3, Kofi Makinwa2,
electrodes (AE), i.e., the combination of dry electrodes with in situ amplification, are increasingly used for biopotential measurements in emerging healthcare and lifestyle applications [1]. Compared to gel-based wet el
Chris Van Hoof3, Refet Firat Yazicioglu1,3 Holst Centre/imec, Eindhove
ISSCC 2014 Session 24 Medical & Bio
An Analog-Digital-Hybrid Single-Chip RX Beamformer with Non-Uniform Sampling for 2D-CMUT Ultrasound Imaging to Achieve Wide Dynamic Range of Delay and Small Chip Area
Ji-Yong Um1, Eun-Woo Song1, Yoon-Jee Kim1, Seong-Eun Cho1,
Min-Kyun Chae1, Jongkeun Song2, Baehyung Kim2, Seunghun Lee2, Jihoon Bang2, Youngil Kim2, Kyungil Cho2, Byungsub Kim1, Jae-Yoon Sim1, Hong-June Park1 Pohang University of Science and Technology, Pohang, Korea, Samsung Ad
ISSCC 2014 Session 26 Other
A 130mW 20Gb/s Half-Duplex Serial Link in 28nm CMOS
Vishnu Balan, Olakanmi Oluwole, Gregory Kodani, Charlie Zhong,
Sanjeev Maheswari, Ratnakar Dadi, Arif Amin, Gautam Bhatia, Peter Mills, Ahmed Ragab, Edward Lee nVidia, Santa Clara, CA As the processing power and clock rate of CPUs and GPUs increase, there is a need for increased I/O
ISSCC 2014 Session 26 Other
A 205mW 32Gb/s 3-Tap FFE/6-Tap DFE Bidirectional Serial Link in 22nm CMOS
James Jaussi1, Ganesh Balamurugan1, Sami Hyvonen1,
Tzu-Chien Hsueh1, Tawfiq Musah1, Gokce Keskin1, Sudip Shekhar1,*, Joseph Kennedy1, Shreyas Sen1, Rajesh Inti1, Mozhgan Mansuri1, Michael Leddige1, Bryce Horine1, Clark Roberts1, Randy Mooney2, Bryan Casper1 Intel, Hillsb
ISSCC 2014 Session 26 Other
A Pin- and Power-Efficient Low-Latency 8-to-12Gb/s/wire 8b8w-Coded SerDes Link for High-Loss Channels in 40nm Technology
Anant Singh1, Dario Carnelli1, Altay Falay1, Klaas Hofstra1,
Fabio Licciardello1, Kia Salimi1, Hugo Santos1, Amin Shokrollahi1, Roger Ulrich1, Christoph Walter1, John Fox2, Peter Hunt2, John Keay2, Richard Simpson2, Andy Stewart2, Giuseppe Surace2, Harm Cronie3 Kandou Bus, Lausann
ISSCC 2014 Session 26 Other
A 25.6Gb/s Differential and DDR4/GDDR5 Dual-Mode Transmitter with Digital Clock Calibration in 22nm CMOS
Tzu-Chien Hsueh, Ganesh Balamurugan, James Jaussi, Sami Hyvonen,
Joseph Kennedy, Gokce Keskin, Tawfiq Musah, Sudip Shekhar*, Rajesh Inti, Shreyas Sen, Mozhgan Mansuri, Clark Roberts, Bryan Casper Intel, Hillsboro, OR *now with University of British Columbia, Vancouver, Canada A wide r
ISSCC 2014 Session 26 Other
An 8-to-16Gb/s 0.65-to-1.05pJ/b 2-Tap ImpedanceModulated Voltage-Mode Transmitter with Fast Power-State Transitioning in 65nm CMOS
Young-Hoon Song1, Hae-Woong Yang1, Hao Li2, Patrick Yin Chiang2,3, Samuel Palermo1
per-channel data-rates and energy efficiency to meet projected system bandwidth demands. These constraints necessitate the design of ultra-low-power serial-link transmitters that can efficiently incorporate equalization
Texas A&M University, College Station, TX, Oregon State University, Co
ISSCC 2014 Session 26 Other
A 2.667Gb/s DDR3 Memory Interface with Asymmetric ODT on Wirebond Package and Single-Side-Mounted PCB
Shang-Pin Chen, Chih-Chien Hung, Qui-Ting Chen, Sheng-Ming Chang,
external environments, such as chip package type and system board design. In order to guarantee the system performance, IP providers often define the package and PCB design constraints to reduce product risks [1]. These
Ming-Shi Liou, Bo-Wei Hsieh, Hsiang-I Huang, Brian Liu, Yan-Bin Luo Me
ISSCC 2014 Session 27 Digital Circuits
A 6mW 5K-Word Real-Time Speech Recognizer Using WFST Models
Michael Price, James Glass, Anantha P. Chandrakasan
Hardware-accelerated speech recognition is needed to supplement today’s cloud-based systems in power- and bandwidth-constrained scenarios such as wearable electronics. With efficient hardware speech decoders, client devi
Massachusetts Institute of Technology, Cambridge, MA
ISSCC 2014 Session 27 Digital Circuits
A 210mV 5MHz Variation-Resilient Near-Threshold JPEG Encoder in 40nm CMOS
Nele Reynders, Wim Dehaene
Operating circuits in the near-threshold region enables large energy savings. However, such circuits also pose many challenges, such as increased delay, unwanted leakage paths and high sensitivity to variations. Working
KU Leuven, Leuven, Belgium
ISSCC 2014 Session 27 Digital Circuits
A 0.75-Million-Point Fourier-Transform Chip for Frequency-Sparse Signals
Omid Abari, Ezz Hamed, Haitham Hassanieh, Abhinav Agarwal,
Dina Katabi, Anantha P. Chandrakasan, Vladimir Stojanovic Massachusetts Institute of Technology, Cambridge, MA Applications like spectrum sensing, radar signal processing, and pattern matching by convolving a signal with
ISSCC 2014 Session 27 Digital Circuits
A Multi-Granularity FPGA with Hierarchical Interconnects for Efficient and Flexible Mobile Computing
Cheng C. Wang1, Fang-Li Yuan1, Tsung-Han Yu2, Dejan Markovic1
Following the rapid expansion of mobile computing in the past decade, mobile system-on-a-chip (SoC) designs have off-loaded most compute-intensive tasks to dedicated accelerators to improve energy efficiency. An increasi
University of California, Los Angeles, CA, 2Qualcomm, Irvine, CA
ISSCC 2014 Session 27 Digital Circuits
An 821MHz 7.9Gb/s 7.3pJ/b/iteration Charge-Recovery LDPC Decoder
Tai-Chuan Ou, Zhengya Zhang, Marios C. Papaefthymiou
This paper presents a 576b LDPC decoder test-chip designed using a chargerecovery logic family. The chip has been fabricated in a 65nm CMOS process and relies on 16 integrated inductors to achieve energy-efficient operat
University of Michigan, Ann Arbor, MI
ISSCC 2014 Session 27 Digital Circuits
A Scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC Decoder for 60GHz Wireless Networks in 28nm UTBB FDSOI
Matthew Weiner1, Milovan Blagojevic1,2,3, Sergey Skotnikov4,
France, 3 EPFL, Lausanne, Switzerland 1 2 Low-density parity-check (LDPC) codes in modern wireless communications are rate- and throughput-scalable, and despite their complexity, decoding them requires low power consumpt
Andreas Burg4, Philippe Flatresse3, Borivoje Nikolic1 University of Ca
ISSCC 2014 Session 27 Digital Circuits
A Static Contention-Free Single-Phase-Clocked 24T Flip-Flop in 45nm for Low-Power Applications
Yejoong Kim, Wanyeong Jung, Inhee Lee, Qing Dong,
solution to stagnating energy efficiencies in digital integrated circuits, arising from slowed voltage scaling in nanometer CMOS [1-2]. The design of sequential elements for NTC, as well as in voltage-scaled systems oper
Michael Henry, Dennis Sylvester, David Blaauw University of Michigan,
ISSCC 2014 Session 28 Wireless
A Programmable 0.7-to-2.7GHz Direct ΔΣ Receiver in 40nm CMOS
Mikko Englund1, Kim B. Östman1, Olli Viitala1, Mikko Kaltiokallio1,
programmable receivers, ideally placing the analog-to-digital converter (ADC) right at the antenna. Such an RF ADC should be tunable over several GHz, have programmable gain, low noise, be blocker-tolerant, and consume m
Kari Stadius1, Kimmo Koli2, Jussi Ryynänen1 Aalto University, Espoo, F
ISSCC 2014 Session 28 Wireless
A 0.29mm2 Frequency Synthesizer in 40nm CMOS with 0.19psrms Jitter and <-100dBc Reference Spur for 802.11ac
Yu-Li Hsueh, Lan-Chou Cho, Chih-Hsien Shen, Yi-Chien Tsai,
alldigital PLLs due to several substantial building blocks such as the loop filter and charge pump (CP). To achieve the required phase noise, the in-band noise is typically suppressed by increasing CP current and loop fi
Tzu-Chan Chueh, Tao-Yao Chang, Jui-Lin Hsu, Jing-Hong Conan Zhan Media
ISSCC 2014 Session 28 Wireless
A Frequency-Defined Vernier Digital-to-Time Converter for Impulse Radar Systems in 65nm CMOS
Yu-Hsien Kao, Chang-Ming Lai, Jen-Ming Wu, Po-Chiun Huang,
multi-path immunity for ranging and localization applications [1], [2]. Impulse radar sends signals with short duration and spreads signal power over a large bandwidth. Favorable features of impulse radar are minor inter
Ping-Hsuan Hsieh, Ta-Shun Chu National Tsing Hua University, Hsinchu,
ISSCC 2014 Session 29 Data Converters
A 5mW CT ΔΣ ADC with Embedded 2nd-Order Active Filter and VGA Achieving 82dB DR in 2MHz BW
Radha Rajan, Shanthi Pavan
IIT Madras, Chennai, India Conventional continuous-time delta-sigma modulator (CTDSM) architectures do not allow independent control of the shape and bandwidth of the signal transfer function (STF), since the STF is simp
ISSCC 2014 Session 29 Data Converters
A 235mW CT 0-3 MASH ADC Achieving -167dBFS/Hz NSD with 53MHz BW
Yunzhi Dong1, Richard Schreier1, Wenhua Yang2,
ADCs in wireless communication infrastructure is increased bandwidth with little or no relaxation in noise density or power consumption. The historical expectation of system designers is a noise spectral density (NSD) of
Sudhir Korrapati2, Ali Sheikholeslami1,3 Analog Devices, Toronto, ON,
ISSCC 2014 Session 29 Data Converters
A 14b 1GS/s RF Sampling Pipelined ADC with Background Calibration Fig. 29.3.4, and the LMS algorithm is used to estimate the correction coefficients using the recursive formula: Gen + k = Gen k − μ × Vd>n − k @ × Vd>n − k @ × Gen  k − VR >n@
Ahmed M. A. Ali1, Huseyin Dinc1, Paritosh Bhoraskar1, Chris Dillon1,
Scott Puckett1, Bryce Gray1, Carroll Speir1, Jonathan Lanford1, David Jarman1, Janet Brunsilius2, Peter Derounian1, Brad Jeffries1, Ushma Mehta1, Matt McShea1, Ho-Young Lee3 Where Vd is the dither value, VR is the residu
ISSCC 2014 Session 3 RF & Wireless
Polar Antenna Impedance Detection and Tuning for Efficiency Improvement in a 3G/4G CMOS Power Amplifier
Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi,
efficiency and achieve a long battery life. Therefore, both the peak efficiency and the efficiency loss due to antenna impedance mismatch or power back-off are highly critical design issues. In particular, the challenge
Yasuhiko Kuriyama, Masami Nagaoka Toshiba, Kawasaki, Japan One of the
ISSCC 2014 Session 3 RF & Wireless
A 1.95GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier with Envelope/Phase Generator and Timing Aligner for WCDMA and LTE
Kazuaki Oishi1, Eiji Yoshida1, Yasufumi Sakai1, Hideki Takauchi1,
Yoichi Kawano1, Noriaki Shirai2, Hideki Kano2, Masahiro Kudo2, Tomotoshi Murakami2, Tetsuro Tamura2, Shigeaki Kawai2, Shinji Yamaura2, Kazuo Suto2, Hiroshi Yamazaki1, Toshihiko Mori1 Fujitsu Laboratories, Kawasaki, Japan
ISSCC 2014 Session 3 AI / ML
A Transformer-Coupled True-RMS Power Detector in 40nm CMOS
Brecht Francois, Patrick Reynaert
To optimize the power consumption and system performance of battery-supplied devices, it is required to monitor and adjust the transmitted RF power accurately and continuously. This is typically done by an external power
KU Leuven, Leuven, Belgium
ISSCC 2014 Session 3 AI / ML
A Dual-Mode Transformer-Based Doherty LTE Power Amplifier in 40nm CMOS
Ercan Kaymaksut, Patrick Reynaert
Modern high-data-rate communication systems such as LTE use spectrally efficient modulation schemes with a high peak-to-average power ratio (PAPR), placing stringent linearity demands on the RF power amplifiers (PA). The
KU Leuven, Leuven, Belgium
ISSCC 2014 Session 3 RF & Wireless
A 1.0-to-2.5GHz Beamforming Receiver with Constant-Gm Vector Modulator Consuming < 9mW per Antenna Element in 65nm CMOS
Michiel C. M. Soer1, Eric A. M. Klumperink1, Bram Nauta1,
Frank E. van Vliet1,2 University of Twente, Enschede, The Netherlands, TNO Science and Industry, The Hague, The Netherlands The inverter transconductor in Fig. 3.5.3 is self-biased, and consists of standardVt transistors
ISSCC 2014 Session 3 RF & Wireless
A Noise-Cancelling Receiver with Enhanced Resilience to Harmonic Blockers
David Murphy, Hooman Darabi, Hao Xu
By employing two passive-mixer-based downconversion paths, the frequencytranslational noise-cancelling receiver (FTNC-RX) achieves a low noise figure and can tolerate most out-of-band blockers up to 0dBm with little perf
Broadcom, Irvine, CA
ISSCC 2014 Session 3 RF & Wireless
A Fully Integrated Highly Reconfigurable DiscreteTime Super-Heterodyne Receiver
Massoud Tohidian, Iman Madadi, Robert Bogdan Staszewski
Since the invention of radio, superheterodyne has been the architecture of choice for receivers (RX). Thanks to its high intermediate-frequency (IF), the problems related to flicker noise, time-varying dc offsets, in-ban
Delft University of Technology, Delft, The Netherlands