ISSCC 2015
Session 4
Digital Processors
A 409GOPS/W Adaptive and Resilient Domino Register File in 22nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection
Droop, Temperature and Aging Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo Aseron, Trang Nguyen Jr, Charles Augustine, James Tschanz, Vivek De Intel, Hillsboro, OR 8-transistor (8T) cell 1-read/1-write (1R1W) register file
ISSCC 2015
Session 4
Digital Processors
A 28nm x86 APU Optimized for Power and Area Efficiency
Jim Farrell1, Dave Johnson2, Guhan Krishnan1, Hugh McIntyre3, Edward McLellan1, Samuel Naffziger2, Russell Schreiber4, Sriram Sundaram4, Jonathan White1 AMD, Boxborough, MA, 2AMD, Fort Collins, CO, 3 AMD, Sunnyvale, CA,
ISSCC 2015
Session 5
Analog Circuits
A 60V Auto-zero and Chopper Operational Amplifier with 800kHz Interleaved Clocks and Input Bias-Current Trimming Yoshinori Kusuda
widely used to support industrial, instrumentation, and other applications [1]. Most of them have been realized with BJT or JFET processes [1] to offer voltage noise PSD better than 10nV/√Hz and offset voltage drift bett
ISSCC 2015
Session 5
Analog Circuits
A 4.7MHz 53µW Fully Differential CMOS Reference Clock Oscillator with –22dB Worst-Case PSNR for Miniaturized SoCs
KAIST, Daejeon, Korea, 3 Daegu Gyeongbuk Institute of Science and Technology, Daegu, Korea 1 2 Low-power CMOS reference clock oscillators have been widely used in miniaturized SoCs for emerging microsystems such as impla
ISSCC 2015
Session 5
Analog Circuits
A 110dB SNR ADC with ±30V Input Common-Mode Range and 8µV Offset for Current Sensing Applications
input common-mode voltage range (CMVR) while powered from a single 5V supply. This beyond-the-rails capability is obtained by employing a capacitively coupled high-voltage (HV) chopper at the input of a switched-capacito
ISSCC 2015
Session 5
Analog Circuits
A 2-Channel -83.2dB Crosstalk 0.061mm2 CCIA with an Orthogonal Frequency Chopping Technique
Area-efficient low-noise instrumentation amplifiers (IAs) are required in various multi-channel sensing and monitoring applications. These IAs must be designed to achieve low noise and low power, good noise efficiency fa
ISSCC 2015
Session 5
Analog Circuits
A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-Low Power Systems
David D. Wentzloff, Benton H. Calhoun PsiKick, Charlottesville, VA Most systems require a voltage reference independent of variation of power supply, process, or temperature, and a bandgap voltage reference (BGR) often s
ISSCC 2015
Session 5
Analog Circuits
A Forward-Body-Bias Tuned 450MHz Gm-C 3rd-Order Low-Pass Filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V Supply
inverter-based Gm-C filters [1,2] allow achieving bandwidths beyond what is possible with opamp-RC techniques. The class-AB behavior of the inverter, together with the high transconductance for a given quiescent current,
ISSCC 2015
Session 5
Analog Circuits
A 0.13µm Fully Digital Low-Dropout Regulator with Adaptive Control and Reduced Dynamic Stability for Ultra-Wide Dynamic Range
An increasing number of power domains and of power states per domain, as well as decreasing decoupling capacitance per local grid and ultra-wide current dynamic range of digital load circuits (for low power on one end wh
ISSCC 2015
Session 5
Analog Circuits
A 29nW Bandgap Reference Circuit
Young-Chul Cho2, Seong-Jin Jang2, Joo Sun Choi2, Byungsub Kim1, Hong-June Park1, Jae-Yoon Sim1 Pohang University of Science and Technology, Pohang, Korea, Samsung Electronics, Hwaseong, Korea 1 2 Bandgap references (BGRs
ISSCC 2015
Session 5
Analog Circuits
A Digitally Assisted Single-Point-Calibration CMOS Bandgap Voltage Reference with a 3σ Inaccuracy of ±0.08% for Fuel-Gauge Applications
Johannes Thielmann, Henrik Hassander, Herbert Gruber, Florian Hus, Christoph Sandner Infineon Technologies, Villach, Austria Accurate voltage references are key building blocks for almost all electronic systems. Specific
ISSCC 2015
Session 5
Analog Circuits
A 37µW Dual-Mode Crystal Oscillator for Single-Crystal Radios
reductions in power, cost and size of wireless sensors. Wireless nodes reduce average power by using intermittent data transmission, which is synchronized by a continuously operating sleep timer in each node. In some app
ISSCC 2015
Session 6
Image Sensors
A 1/1.7-inch 20Mpixel Back-Illuminated Stacked CMOS Image Sensor for New Imaging Applications
Naoki Kawazu1, Chihiro Okada1, Takumi Oka1, Kensuke Koiso2, Atsushi Masagaki1, Yoichi Yagasaki3, Shigeru Gonoi4, Tatsuya Ichikawa1, Masatoshi Mizuno5, Tatsuya Sugioka1, Takafumi Morikawa1, Yoshiaki Inada1, Hayato Wakabay
ISSCC 2015
Session 6
Image Sensors
133Mpixel 60fps CMOS Image Sensor with 32-Column Shared High-Speed Column-Parallel SAR ADCs
Jeff Rysinski2, David Estrada2, Shi Yan2, Takuji Soeno1, Tomohiro Nakamura1, Tetsuya Hayashida1, Hiroshi Shimamoto1, Barmak Mansoorian2 NHK Science & Technology Research Laboratories, Tokyo, Japan Forza Silicon, Pasadena
ISSCC 2015
Session 6
Image Sensors
A 45.5μW 15fps Always-On CMOS Image Sensor for Mobile and Wearable Devices
Most mobile devices embed a CMOS image sensor (CIS) for capturing images. In addition, a variety of sensors such as proximity, ambient light, and fingerprint sensors are integrated for device control. The integration of
ISSCC 2015
Session 6
Image Sensors
Single-Shot 200Mfps 5×3-Aperture Compressive CMOS Imager
Industries, Hamamatsu, Japan 1 2 Ultra-high-speed cameras are a powerful tool for biology as well as physics and mechanics to analyze the process of ultra-high-speed phenomena. The frame rate of the state-of-the-art burs
ISSCC 2015
Session 6
Image Sensors
μW at 60fps 240×160-Pixel Vision Sensor for Motion Capturing with In-Pixel Non-Volatile Analog Memory Using Crystalline Oxide Semiconductor FET
Munehiro Kozuma1, Seiichi Yoneda1, Hiroki Inoue1, Yoshiyuki Kurokawa1, Takayuki Ikeda1, Yoshinori Ieda1, Naoto Yamade1, Hidekazu Miyairi1, Makoto Ikeda2, Shunpei Yamazaki1 Semiconductor Energy Laboratory, Kanagawa, Japan
ISSCC 2015
Session 6
Image Sensors
A 240Hz-Reporting-Rate Mutual-Capacitance Touch-Sensing Analog Front-End Enabling Multiple Active/Passive Styluses with 41dB/32dB SNR for 0.5mm Diameter
A mutual-capacitance touch-sensing architecture and a system that enables concurrent usage of multiple active styluses having different properties such as color, thickness, shape, etc., are developed and verified with us
ISSCC 2015
Session 6
Image Sensors
A 2.3mW 11cm-Range Bootstrapped and Correlated-Double-Sampling (BCDS) 3D Touch Sensor for Mobile Devices
with displays, offer many advantages over that of conventional touch-panel screens by offering a more hygienic and a more immersive & interactive human/machine interface for 3D user experiences [1]. While significant pro
ISSCC 2015
Session 6
Image Sensors
A Pen-Pressure-Sensitive Capacitive Touch System Using Electrically Coupled Resonance Pen
become widely used in mobile devices such as smartphones, tablets, and so on. Beyond ordinary touch functions, some devices adopt an extra electromagnetic resonance (EMR) system [1] to support pens for advanced user expe
ISSCC 2015
Session 7
Memory
A Low-Power 64Gb MLC NAND-Flash Memory in 15nm CMOS Technology
Kazuyoshi Muraoka1, Masaki Fujiu1, Fumihiro Kouno1, Michio Nakagawa1, Masami Masuda1, Koji Kato1, Yuri Terada1, Yuki Shimizu1, Mitsuaki Honma1, Akihiro Imamoto1, Tomoko Araya1, Hayato Konno1, Takuya Okanaga1, Tomofumi Fu
ISSCC 2015
Session 7
Memory
A 128Gb 3b/cell V-NAND Flash Memory with 1Gb/s I/O Rate
Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, You-Se Kim, Hyun-Wook Park, Dong-Hun Kwak, Sang-Won Park, Seok-Min Yoon, Wook-Ghee Hahn, Jin-Ho Ryu, Sang-Won Shim, Kyung-Tae Kang, Sung-Ho Choi, Jeong-Don Ihm,
ISSCC 2015
Session 7
Memory
A 28nm Embedded SG-MONOS Flash Macro for Automotive Achieving 200MHz Read Operation and 2.0MB/s Write Throughput at Tj of 170°C
Accelerated advances in automotive technology, such as sophisticated real-time engine controls for higher fuel efficiency and advanced driver-assistance systems (ADAS), are expanding the application range of Flash MCUs,
ISSCC 2015
Session 7
Memory
A Covalent-Bonded Cross-Coupled Current-Mode Sense Amplifier for STT-MRAM with 1T1MTJ Common Source-Line Structure Array
candidate for next-generation universal memory technology with high density, high-speed access time, and nonvolatile characteristics. Due to good scalability of the magnetic tunnel junction (MTJ) cell in sub-20nm technic
ISSCC 2015
Session 7
Memory
A 3.3ns-Access-Time 71.2μW/MHz 1Mb Embedded STT-MRAM Using Physically Eliminated Read-Disturb Scheme and Normally-Off Memory Architecture
Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita Toshiba, Kawasaki, Japan Nonvolatile memory, spin-transfer torque magnetoresistive RAM (STT-MRAM) is being devel
ISSCC 2015
Session 7
Memory
1GB/s 2Tb NAND Flash Multi-Chip Package with Frequency-Boosting Interface Chip and low-to-high hysteresis by implementing MN4 and MN3, respectively, to block the extra toggle.
Joon-Ho Shin, Chae-Hoon Kim, Seung-Woo Yu, Ji-Yeon Shin, Seon-Kyoo Lee, Devraj Rajagopal, Sang-Tae Kim, Kyeong-Tae Kang, Jeong-Joon Park, Yong-Jin Kwon, Min-Jae Lee, Sung-Hoon Kim, Seung-Hoon Shin, Hyung-Gon Kim, Jin-Tae
ISSCC 2015
Session 7
Memory
Enterprise-Grade 6× Fast Read and 5× Highly Reliable SSD with TLC NAND-Flash Memory for Big-Data Storage
techniques that achieve high speed and high reliability. Quick low-density parity-check (LDPC) reduces the read latency of 1Xnm TLC NAND Flash SSD by 83%. Dynamic VTH optimization and auto data recovery reduce the NAND F
ISSCC 2015
Session 8
Digital Circuits
An 80nW Retention 11.7pJ/Cycle Active Subthreshold ARM Cortex-M0+ Subsystem in 65nm CMOS for WSN Applications
Pranay Prabhat, David Flynn ARM, Cambridge, United Kingdom The Internet of Things is widely expected to comprise billions of connected devices, many of which will be wireless sensor nodes (WSN). One challenge this poses
ISSCC 2015
Session 8
Digital Circuits
Batteryless Sub-nW Cortex-M0+ Processor with Dynamic Leakage-Suppression Logic
Recent low-voltage design techniques have enabled dramatic improvements in miniaturization and lifetime of wireless sensor nodes [1-3]. These systems typically use a secondary battery to provide energy when the sensor is
ISSCC 2015
Session 8
Digital Circuits
A 10.5μA/MHz at 16MHz Single-Cycle Non-Volatile Memory Access Microcontroller with Full State Retention at 108nA in a 90nm Process
is an everincreasing demand for lowering power dissipation, especially for sensor nodes, where low energy consumption translates to longer battery life or operation with a smaller/cheaper battery. At the heart of a senso
ISSCC 2015
Session 8
Digital Circuits
A 0.33V/-40°C Process/Temperature Closed-Loop Compensation SoC Embedding All-Digital Clock Multiplier and DC-DC Converter Exploiting FDSOI 28nm Back-Gate Biasing
Jean-Marc Daveau1, Cyril Bottoni1, David Bol4, Julien De-Vos4, Dominique Zamora5, Benjamin Coeffic1, Dimitri Soussan1, Damien Croain1, Mehdi Naceur6, Pierre Schamberger6, Philippe Roche1, Dennis Sylvester3 STMicroelectro
ISSCC 2015
Session 8
Digital Circuits
A 16nm Auto-Calibrating Dynamically Adaptive Clock Distribution for Maximizing Supply-Voltage-Droop Tolerance Across a Wide Operating Range
supply voltage (VDD) droops when the current in the power delivery network abruptly changes in response to workload variations, thus degrading performance and energy efficiency. Previous adaptive circuit techniques aim t
ISSCC 2015
Session 8
Digital Circuits
Enabling Wide Autonomous DVFS in a 22nm Graphics Execution Core Using a Digitally Controlled Hybrid LDO/Switched-Capacitor VR with Fast Droop Mitigation
Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De Intel, Hillsboro, OR A graphics execution core in 22nm improves energy effic
ISSCC 2015
Session 8
Digital Circuits
Dual-Use Low-Drop-Out Regulator / Power Gate with Linear and On-Off Conduction Modes for Microprocessor On-Die Supply Voltages in 14nm
In recent generations of microprocessors, there has been an increase in the number and types of processors integrated on the same die. For example, in [1] several IA (Intel architecture) cores have been integrated on-chi
ISSCC 2015
Session 9
Wireless
A 13mm2 40nm Multiband GSM/EDGE/HSPA+/TDSCDMA/LTE Transceiver
Iason Vassiliou1, Charalampos Kapnistis1, Yiannis Kokolakis1, Hamed Peyravi1, Gerasimos Theodoratos1, Konstantinos Vryssas1, Nikos Kanakaris1, Christos Kokozidis1, Spyros Kavadias1, Sofoklis Plevridis1, Paul Mudge2, Igor
ISSCC 2015
Session 9
Wireless
A Single-Chip HSPA Transceiver with Fully Integrated 3G CMOS Power Amplifiers
Peter Pfann1, Ronald Thüringer1, Martin Kastner1, Christian Pröll2, Andreas Schwarz2, Florian Mrugalla1, Jimena Saporiti2, Umut Basaran3, Andreas Langer1, Tobias D. Werth1, Timo Gossmann1, Boris Kapfelsperger1, Johann Pl
ISSCC 2015
Session 9
Wireless
A Transmitter with 10b 128MS/s Incremental-ChargeBased DAC Achieving -155dBc/Hz Out-of-Band Noise
stringent requirements on every transmitter design aspect. Especially when the inter-stage SAW filter is removed, FDD operation using high-order modulation schemes (as in e.g. WCDMA, LTE) demands both remarkable noise pe
ISSCC 2015
Session 9
Wireless
A 28nm CMOS Digital Fractional-N PLL with -245.5dB FOM and a Frequency Tripler For 802.11abgn/ac Radio
Arvind Anumula Paramanandam, Anuranjan Jha, Norman Liu, Edwin Chan, Li Lin Marvell, Santa Clara, CA The fast adaptation of WiFi 802.11ac 256-QAM mode requires RF clocks with very low integrated phase error to deliver goo
ISSCC 2015
Session 9
Wireless
Efficient Digital Quadrature Transmitter Based on IQ Cell Sharing
employ various modulation methods in various frequency bands, interest in the software-defined radio (SDR) transceiver to support the standards is increasing. For the flexible transceiver, a digital-intensive transmitter
ISSCC 2015
Session 9
Wireless
A 5.3GHz 16b 1.75GS/s Wideband RF Mixing-DAC Achieving IMD<-82dBc up to 1.9GHz
infrastructure require both high linearity and large bandwidth (BW) at GHz frequencies. The combination of multicarrier GSM, WCDMA and LTE typically requires IMD<-80dBc and SFDR>80dBc in a large transmit bandwidth of 300
ISSCC 2015
Session 9
Wireless
An LTE SAW-Less Transmitter Using 33% Duty-Cycle LO Signals for Harmonic Suppression
With limited frequency allocation in the radio spectrum, spectral efficiency has always been the core development of communication systems. To accommodate the increase in demand for wireless data services, RF systems hav
← 上一页 · 第 4/4 页 · 共 191 篇