ISSCC 2016
Session 3
Wireline I/O
A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI
electrical link technology to support 400Gb/s standards is underway [1-5]. Physical constraints paired to the small area available to dissipate heat, impose limits to the maximum number of serial interfaces and therefore
ISSCC 2016
Session 3
Wireline I/O
A 40-to-64Gb/s NRZ Transmitter with SupplyRegulated Front-End in 16nm FinFET
Jin Namkoong, Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang Xilinx, San Jose, CA Due to increasing bandwidth demand in data centers and telecommunication infrastructures, the maximum data-rate of wireline transceivers i
ISSCC 2016
Session 4
Digital Processors
14nm 6th-Generation Core Processor SoC with Low Power Consumption and Improved Performance
Muhammad Abozaed, Yair Talker, Ziv Shmuely, Saher Abu Rahme transitions in the victim neighborhood circuits should not exceed a crosstalk limit during normal operation. Another parameter that must be factored is reliabil
ISSCC 2016
Session 4
Digital Processors
Increasing the Performance of a 28nm x86-64 Microprocessor Through System Power Management
Ravinder Rachala1, Sriram Sambamurthy1, Steven Liepe2, Miguel Rodriguez2, Tom Burd3, Adam Clark4, Michael Austin1, Samuel Naffziger2 AMD, Austin, TX, AMD, Fort Collins, CO, 3 AMD, Sunnyvale, CA, 4 AMD, Markham, ON, Canad
ISSCC 2016
Session 4
Digital Processors
A 20nm 2.5GHz Ultra-Low-Power Tri-Cluster CPU Subsystem with Adaptive Power Allocation for Optimal Mobile SoC Performance
C.J. Chung1, Sumanth Gururajarao1, Ping Kao2, Anand Rajagopalan1, Anirban Saha3, Amit Jain4, Ericbill Wang2, Shichin Ouyang5, Huajun Wen1, Achuta Thippana1, HsinChen Chen1, Syed Rahman1, Minh Chau1, Anshul Varma1, Brian
ISSCC 2016
Session 4
Digital Processors
A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC for Car Information Systems
Chi Lan Phuong Nguyen2, Tetsuya Shibayama1, Kenichi Iwata1, Katsuya Mizumoto1, Takahiro Irita3, Hirotaka Hara3, Toshihiro Hattori1 Renesas System Design, Tokyo, Japan, Renesas Design Vietnam, Ho Chi Minh City, Vietnam, 3
ISSCC 2016
Session 4
Digital Processors
A 16nm FinFET Heterogeneous Nona-Core SoC Complying with ISO26262 ASIL-B: Achieving 10-7 Random Hardware Failures per Hour Reliability
car information systems (commonly referred to as car infotainment) is expanding from dedicated navigation systems to joint car-cockpit systems, including the dashboard meter, telematics for the internet/cloud, and advanc
ISSCC 2016
Session 4
Digital Processors
A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V Shared Logarithmic Floating Point Unit for Acceleration of Nonlinear Function Kernels in a Tightly Coupled Processor Cluster
many application areas, such as IoT and wearables. While for some applications, integer and fixed-point processor instructions suffice, others (e.g. simultaneous localization and mapping – SLAM, stereo vision, nonlinear
ISSCC 2016
Session 4
Digital Processors
A 65nm ReRAM-Enabled Nonvolatile Processor with 6× Reduction in Restore Time and 4× Higher Clock Frequency Using Adaptive Data Retention and Self-Write-Termination Nonvolatile Logic
Zhe Yuan1, Chien-Chen Lin2, Qi Wei1, Yu Wang1, Ya-Chin King2, Chrong-Jung Lin2, Pedram Khalili3, Kang-Lung Wang3, Meng-Fan Chang2, Huazhong Yang1 Tsinghua University, Beijing, China, National Tsing Hua University, Hsinch
ISSCC 2016
Session 5
Analog Circuits
A 10MHz-Bandwidth 4µs-Large-Signal-Settling 6.5nV/√Hz-Noise 2µV-Offset Chopper Operational Amplifier
Low-offset and low-noise operational amplifiers (OpAmps) are essential for precision measurement systems. Applications such as precision weigh scales, sensor front-ends, bridge transducers, interfaces for thermocouple se
ISSCC 2016
Session 5
Analog Circuits
A 1.4V 10.5MHz Swing-Boosted Differential Relaxation Oscillator with 162.1dBc/Hz FOM and 9.86psrms Period Jitter in 0.18μm CMOS
Daegu Gyeongbuk Institute of Science and Technology, Daegu, Korea, 3 Nanyang Technological University, Singapore, Singapore 1 2 Relaxation oscillators have a profound scope as on-chip reference clock sources or sensor fr
ISSCC 2016
Session 5
Analog Circuits
A 118dB-PSRR 0.00067%(-103.5dB) THD+N and 3.1W Fully Differential Class-D Audio Amplifier with PWM Common-Mode Control
A high power-supply rejection ratio (PSRR) and high-linearity Class-D audio amplifier (CDA) becomes important as the CDA is directly connected to a battery supply for efficiency considerations in mobile phone application
ISSCC 2016
Session 5
Analog Circuits
A 2×70W Monolithic Five-Level Class-D Audio Power Amplifier
Thomas Holm Hansen1, Allan Nogueras Nielsen1,2, Hans Hasselby-Andersen1 Merus Audio, Herlev, Denmark, Now at Knowles Corporation, Roskilde, Denmark 1 2 The consumer electronics trends of miniaturization and portability h
ISSCC 2016
Session 5
Analog Circuits
A Sub-μW 36nV/√Hz Chopper Amplifier for Sensors Using a Noise-Efficient Inverter-Based 0.2V-Supply Input Stage
In low-bandwidth, low-noise applications of wireless sensor nodes, the sensor front-end amplifier presents a power-consumption bottleneck since its current draw is noise-limited and cannot be scaled with the low data-rat
ISSCC 2016
Session 5
Analog Circuits
A 2µW 40mVpp Linear-Input-Range ChopperStabilized Bio-Signal Amplifier with Boosted Input Impedance of 300MΩ and Electrode-Offset Filtering
Modern neuromodulation requires closed-loop functionality, where neural recordings are used to adapt stimulation patterns in real time. A closed-loop system requires the neural sensing front-end to record small neural si
ISSCC 2016
Session 5
Analog Circuits
A 420μW 100GHz-GBW CMOS ProgrammableGain Amplifier Leveraging the Cross-Coupled Pair Regeneration
Cross-coupled pairs are certainly among the most widely adopted fundamental circuits still in use today. This elegant device arrangement yields broadband positive feedback with high gain and low power, desirable features
ISSCC 2016
Session 5
Analog Circuits
A 39.25MHz 278dB-FOM 19µW LDO-Free Stacked-Amplifier Crystal Oscillator (SAXO) Operating at I/O Voltage
frequency of 12Hz. The active resistor of 27MΩ with a size of 1800μm2 is achieved with a multiplication of RBIAS (= 80kΩ) by (W/L)M1 / (W/L)M3. 500pF is achieved with a multiplication of CLPF (= 50pF) by the gain (≈ 10)
ISSCC 2016
Session 5
Analog Circuits
A 4.7nW 13.8ppm/°C Self-Biased Wakeup Timer Using a Switched-Resistor Scheme
under restricted battery capacity due to their size [1]. Due to low duty cycles in many sensing applications, sleep-mode power can dominate the total energy budget. Wakeup timers are a key always-on component in such sle
ISSCC 2016
Session 5
Analog Circuits
A 24MHz Crystal Oscillator with Robust Fast Start-Up Using Dithered Injection
Wireless nodes in Internet-of-Everything (IoE) applications achieve low power consumption by operating the radio at very low duty cycles. The wireless node spends most of its time in sleep, waking only occasionally to tr
ISSCC 2016
Session 6
Image Sensors
An Over 120dB Simultaneous-Capture WideDynamic-Range 1.6e- Ultra-Low-Reset-Noise Organic-Photoconductive-Film CMOS Image Sensor
Masaaki Yanagida, Tokuhiko Tamaki, Masayuki Takase, Hidenari Kanehara, Masashi Murakami, Yasunori Inoue Panasonic, Moriguchi, Japan Image sensors are increasingly becoming key devices for various applications (in-vehicle
ISSCC 2016
Session 6
Image Sensors
210ke- Saturation Signal 3µm-Pixel VariableSensitivity Global-Shutter Organic Photoconductive Image Sensor for Motion Capture
in-vehicle cameras, and surveillance cameras require a global shutter (GS) function. GS functions are an increasingly powerful technology driver, not only for solving imaging problems caused by rolling shutter distortion
ISSCC 2016
Session 6
Image Sensors
105×65mm2 391Mpixel CMOS Image Sensor with >78dB Dynamic Range for Airborne Mapping Applications
Bart Ceulemans, Guy Meynants, Navid Sarhangnejad, Gavril Arsinte, Victor Statescu, Sonja van der Groen CMOSIS NV, Antwerp, Belgium In today’s airborne mapping applications, there is a strong push towards higher-resolutio
ISSCC 2016
Session 6
Image Sensors
An APS-H-Size 250Mpixel CMOS Image Sensor Using Column Single-Slope ADCs with Dual-Gain Amplifiers
Daisuke Yoshida, Yasushi Matsuno, Masanobu Ohmura, Hidekazu Takahashi, Katsuhito Sakurai, Takeshi Ichikawa, Hiroshi Yuzurihara, Shunsuke Inoue Canon, Kawasaki, Japan Recently, there has been strong demand for high-resolu
ISSCC 2016
Session 6
Image Sensors
A 64×64-Pixel Digital Silicon Photomultiplier Direct ToF Sensor with 100MPhotons/s/pixel Background Rejection and Imaging/Altimeter Mode with 0.14% Precision up to 6km for Spacecraft Navigation and Landing
Recent technology surveys identified flash light detection and ranging technology as the best choice for the navigation and landing of spacecrafts in extraplanetary missions, working from single-point altimeter to range-
ISSCC 2016
Session 6
Image Sensors
A 1280×720 Single-Photon-Detecting Image Sensor with 100dB Dynamic Range Using a Sensitivity-Boosting Technique
sensors such as camcorders, digital still cameras, mobile phones, and surveillance cameras. Even though leading-edge image sensors have reached the noise floor of a few electrons [1,2], a thrust towards darker levels sti
ISSCC 2016
Session 6
Image Sensors
A 1.2e- Temporal Noise 3D-Stacked CMOS Image Sensor with Comparator-Based Multiple-Sampling PGA
2e-, 3D-stacked CMOS image sensor (CIS) for mobile applications. A key motivation for using a stacked configuration is to minimize the chip area. Also, since numerous components must be integrated into the bottom chip, a
ISSCC 2016
Session 6
Image Sensors
A 1.5V 33Mpixel 3D-Stacked CMOS Image Sensor with Negative Substrate Bias
image sensors. In addition, 3D stacking separates pixel array and peripheral circuits. As such, computational imaging blocks (stereo vision, array camera, reconfigurable instruction cell array, etc.) can integrate with s
ISSCC 2016
Session 6
Image Sensors
A 1.1µm 33Mpixel 240fps 3D-Stacked CMOS Image Sensor with 3-Stage Cyclic-Based Analogto-Digital Converters
Hiroshi Shimamoto1, Tomohiko Kosugi2, Sungwook Jun2, Satoshi Aoyama2, Ming-Chieh Hsu3, Yuichiro Yamashita3, Hirofumi Sumi3, Shoji Kawahito2,4 NHK Science & Technology Research Laboratories, Tokyo, Japan, Brookman Technol
ISSCC 2016
Session 7
Memory
256Gb 3b/Cell V-NAND Flash Memory with 48 Stacked WL Layers
Yong Sung Cho, Kyung-Tae Kang, Jinho Ryu, Kyung-Min Kang, Sungyeon Lee, Wandong Kim, Hanjun Lee, Jaedoeg Yu, Nayoung Choi, Dong-Su Jang, Jeong-Don Ihm, Doogon Kim, Young-Sun Min, Moo-Sung Kim, An-Soo Park, Jae-Ick Son, I
ISSCC 2016
Session 7
Memory
4Mb STT-MRAM-Based Cache with MemoryAccess-Aware Power Optimization and WriteVerify-Write / Read-Modify-Write Scheme
Keiichi Kushida1, Atsushi Kawasumi1, Hiroyuki Hara1, Keiko Abe1, Naoharu Shimomura1, Junichi Ito1, Shinobu Fujita1, Takashi Nakada2, Hiroshi Nakamura2 Toshiba, Kawasaki, Japan, University of Tokyo, Tokyo, Japan 1 2 Two p
ISSCC 2016
Session 7
Memory
A Resistance-Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage-Class Memory Applications
Tzu-Hsiang Su1,3, Keng-Hao Yang3, Tien-Fu Chen3, Tien-Yen Wang1, Hsiang-Pang Li1, Matthew BrightSky4, SangBum Kim4, Hsiang-Lam Lung1, Chung Lam4 Macronix International, Hsinchu, Taiwan, National Tsing Hua University, Hsi
ISSCC 2016
Session 7
Memory
A 256b-Wordlength ReRAM-based TCAM with 1ns Search-Time and 14× Improvement in WordLength-EnergyEfficiency-Density Product using 2.5T1R cell
Yen-Ning Chiang1, Hsiang-Jen Tsai3, Geng-Hau Yang3, Ya-Chin King1, Chrong Jung Lin1, Tien-Fu Chen3, Meng-Fan Chang1 National Tsing Hua University, Hsinchu, Taiwan, TSMC, Hsinchu, Taiwan, 3 National Chiao Tung University,
ISSCC 2016
Session 7
Memory
A 128Gb 2b/cell NAND Flash Memory in 14nm Technology with tPROG=640μs and 800MB/s I/O Rate
Sung-won Yun, Min-su Kim, Jong-hoon Lee, Minseok Kim, Kangbin Lee, Taeeun Kim, Byungkyu Cho, Dooho Cho, Sangbum Yun, Jung-no Im, Hyejin Yim, Kyung-hwa Kang, Suchang Jeon, Sungkyu Jo, Yang-lo Ahn, Sung-Min Joe, Suyong Kim
ISSCC 2016
Session 7
Memory
A 90nm Embedded 1T-MONOS Flash Macro for Automotive Applications with 0.07mJ/8kB Rewrite Energy and Endurance Over 100M Cycles Under Tj of 175°C
Takashi Hashimoto2, Hideaki Yamakoshi2, Shinichiro Abe2, Takashi Kono1, Yasuhiko Taito1, Takashi Ito1, Takashi Krafuji1, Kenji Noguchi1, Hideto Hidaka1, Tadaaki Yamauchi1 Renesas Electronics, Kodaira, Japan, Renesas Elec
ISSCC 2016
Session 7
Memory
A 768Gb 3b/cell 3D-Floating-Gate NAND Flash Memory
Koichi Kawai1, Jae-Kwan Park2, Shigekazu Yamada1, Feng Pan2, Yuichi Einaga1, Ali Ghalam2, Toru Tanzawa1, Jason Guo2, Takaaki Ichikawa1, Erwin Yu2, Satoru Tamada1, Tetsuji Manabe1, Jiro Kishimoto1, Yoko Oikawa1, Yasuhiro
ISSCC 2016
Session 8
Digital Circuits
A 4×4×2 Homogeneous Scalable 3D Network-on-Chip Circuit with 326MFlit/s 0.66pJ/b Robust and Fault-Tolerant Asynchronous 3D Links
Christian Bernard1, Florian Darve1, Didier Lattard1, Ivan Miro-Panades1, Cristiano Santos1, Fabien Clermidy1, Severine Cheramy1, Frederic Petrot2, Eric Flamand3, Jean Michailos4 CEA-LETI-MINATEC, Grenoble, France, Tima L
ISSCC 2016
Session 8
Digital Circuits
Fully Integrated Low-Drop-Out Regulator Based on Event-Driven PI Control
Modern SoC designs employ a number of power domains, many of which are often implemented by low-drop-out (LDO) regulators. The key overhead of the existing LDO design is the large off-chip output capacitor (Cout) for com
ISSCC 2016
Session 8
Digital Circuits
A 200mA Digital Low-Drop-Out Regulator with Coarse-Fine Dual Loop in Mobile Application Processors
Tae-Hwang Kong2, Dae-Yong Kim2, Kwang-Ho Kim2, Sang-Ho Kim2, Jae-Jin Park2, Ho-Jin Park2, Gyu-Hyeong Cho1 KAIST, Daejeon, Korea, Samsung Electronics, Hwaseong, Korea 1 2 A modern mobile application processor (AP) require
ISSCC 2016
Session 8
Digital Circuits
Post-Silicon Voltage-Guard-Band Reduction in a 22nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating
circuits to lower intrinsic VMIN, retention flops to reduce leakage power during stall periods, and a fully integrated hybrid digital LDO/SCVR regulator to provide a cost-effective means to realize autonomous DVFS under
ISSCC 2016
Session 8
Digital Circuits
A 60%-Efficiency 20nW-500μW Tri-Output Fully Integrated Power Management Unit with Environmental Adaptation and Load-Proportional Biasing for IoT Systems
Seokhyeon Jeong1, Kaiyuan Yang1, Myungjoon Choi1, ZhiYoong Foo1, Suyoung Bang1, Sechang Oh1, Dennis Sylvester1, David Blaauw1 University of Michigan, Ann Arbor, MI, 2Korea University, Seoul, Korea 1 As Internet-of-Things
ISSCC 2016
Session 8
Digital Circuits
A 6.5-to-23.3fJ/b/mm Balanced ChargeRecycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring
Stephen G. Tell1, Thomas H. Greer III1, C. Thomas Gray1, William J. Dally2 Nvidia, Durham, NC, 2Nvidia, Santa Clara, CA 1 Signaling over chip-scale global interconnect is consuming a larger fraction of total power in lar
ISSCC 2016
Session 8
Digital Circuits
Physically Unclonable Function for Secure Key Generation with a Key Error Rate of 2E-38 in 45nm Smart-Card Chips
keys or chip IDs based on intrinsic properties of each chip itself [1-2]. PUFs are a step forward to improve the security level compared to traditional NVM (nonvolatile memory) solutions (FUSEs, EEPROM/FLASH, etc.) becau
ISSCC 2016
Session 8
Digital Circuits
iRazor: 3-Transistor Current-Based Error Detection and Correction in an ARM Cortex-R4 Processor
M. Alioto2, D. Blaauw1, D. Sylvester1 University of Michigan, Ann Arbor, MI, National University of Singapore, Singapore, Singapore 1 2 It is well known that technology scaling has led to increasing process/voltage/tempe
ISSCC 2016
Session 9
Wireless
A 45nm CMOS RF-to-Bits LTE/WCDMA FDD/TDD 2×2 MIMO Base-Station Transceiver SoC with 200MHz RF Bandwidth
S. Uppathil1, S. Kaylor1, A. Akour1, V. Wang1, M. Fares1, F. Dulger1, A. Frank1, D. Ghosh1, S. Madhavapeddi1, H. Safiri1, J. Mehta1, A. Jain1, H. Choo1, E. Zhang1, C. Sestok1, C. Fernando1, Rajagopal K.A. 2, S. Ramakrish
ISSCC 2016
Session 9
Wireless
A Scalable 0.1-to-1.7GHz Spatio-SpectralFiltering 4-Element MIMO Receiver Array with Spatial Notch Suppression Enabling Digital Beamforming
Oregon State University, Corvallis, OR 1 2 Multiple-antenna receivers offer numerous advantages over single-antenna receivers, including sensitivity improvement, ability to reject interferers spatially and enhancement of
ISSCC 2016
Session 9
Wireless
A Very-Low-Noise Frequency-Translational Quadrature-Hybrid Receiver for Carrier Aggregation
To meet the demands of ever-increasing data throughput, carrier aggregation (CA) across frequency bands is becoming necessary. Different regional spectrum allocations lead to a large number of band combinations and chall
ISSCC 2016
Session 9
Wireless
A 2×2 WLAN and Bluetooth Combo SoC in 28nm CMOS with On-Chip WLAN Digital Power
Renaldi Winoto1, Ashkan Olyaei1, Mohammad Hajirostam1, Wai Lau1, Xiang Gao1, Arnab Mitra1, Ovidiu Carnu1, Philip Godoy1, Luns Tee1, Hao Li1, Erdem Erdogan1, Alden Wong1, Qiang Zhu1, Timothy Loo1, Fan Zhang1, Liwei Sheng1
ISSCC 2016
Session 9
Wireless
A Dual-Band Digital-WiFi 802.11a/b/g/n Transmitter SoC with Digital I/Q Combining and Diamond Profile Mapping for Compact Die Area and Improved Efficiency in 40nm CMOS
Dimitris Papadopoulos1, Bryan Huang1, Ray Chen1, Hua Wang1, WH Hsu2, CH Wu2, Osama Shanaa1 MediaTek, San Jose, CA, MediaTek, Hsinchu, Taiwan 1 2 Digital transmitters (DTX) have gained interest in the past few years becau
ISSCC 2016
Session 9
Wireless
A Self-Calibrated 10Mb/s Phase Modulator
-246.6dB-FOM, Fractional-N Subsampling PLL Nereo Markulic1,2, Kuba Raczkowski1, Ewout Martens1, Pedro Emiliano Paro Filho1,2, Benjamin Hershberg1, Piet Wambacq1,2, Jan Craninckx1 imec, Leuven, Belgium, Vrije Universiteit
ISSCC 2016
Session 9
Wireless
Receiver with Integrated Magnetic-Free N-Path-Filter-Based Non-Reciprocal Circulator and Baseband Self-Interference Cancellation for Full-Duplex Wireless
Full-duplex (FD) is an emergent wireless communication paradigm where the transmitter (TX) and the receiver (RX) operate at the same time and at the same frequency. The fundamental challenge with FD is the tremendous amo
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