ISSCC 2016

2016

200 篇论文 · Wireless (30) · RF & Wireless (25) · Wireline I/O (22) · Data Converters (16) · Digital Circuits (16)

ISSCC 2016 Session 22 RF & Wireless
A 172µW Compressive Sampling Photoplethysmographic Readout with Embedded Direct Heart-Rate and Variability Extraction from Compressively Sampled Data
Pamula Venkata Rajesh1,2, Jose Manuel Valero-Sarmiento3,
Long Yan1, Alper Bozkurt3, Chris Van Hoof1,2, Nick Van Helleputte1, Refet Firat Yazicioglu1, Marian Verhelst2 imec, Leuven, Belgium, 2KU Leuven, Leuven, Belgium, North Carolina State University, Raleigh, NC 1 3 Heart rat
ISSCC 2016 Session 22 RF & Wireless
A 0.5V 55µW 64×2-Channel Binaural Silicon Cochlea for Event-Driven Stereo-Audio Sensing
Minhao Yang, Chen-Han Chien, Tobias Delbruck, Shih-Chii Liu
Event-driven DSPs have the advantage of activity-dependent power consumption
ISSCC 2016 Session 22 RF & Wireless
A 22V Compliant 56µW Active Charge Balancer Enabling 100% Charge Compensation even in Monophasic and 36% Amplitude Correction in Biphasic Neural Stimulators
Natalie Butz1, Armin Taschwer2, Yiannos Manoli1,2,3,
Cluster of Excellence, Freiburg, Germany 1 2 Functional electrical stimulation (FES) is a technique that stimulates nerves by electrical charge, but carries the risk of charge accumulation, voltage pile-up, electrode cor
ISSCC 2016 Session 22 RF & Wireless
A 966-Electrode Neural Probe with 384 Configurable Channels in 0.13µm SOI CMOS
Carolina Mora Lopez1, Srinjoy Mitra1, Jan Putzeys1,
Bogdan Raducanu1,2, Marco Ballini1, Alexandru Andrei1, Simone Severi1, Marleen Welkenhuysen1, Chris Van Hoof1,2, Silke Musa1, Refet Firat Yazicioglu1 imec, Leuven, Belgium, 2KU Leuven, Heverlee, Belgium 1 In vivo recordi
ISSCC 2016 Session 22 RF & Wireless
Multi-Functional Microelectrode Array System Featuring 59,760 Electrodes, 2048
Electrophysiology Channels, Impedance and, Neurotransmitter Measurement Units
Vijay Viswam, Jelena Dragas, Amir Shadmani, Yihui Chen, Alexander Stettler, Jan Müller, Andreas Hierlemann ETH Zurich, Basel, Switzerland Various CMOS-based micro-electrode arrays (MEAs) have been developed in recent yea
ISSCC 2016 Session 23 Wireline I/O
A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b Source Synchronous Transceiver Using DVFS and Rapid On/Off in 65nm CMOS
Guanghua Shu, Woo-Seok Choi, Saurabh Saxena,
Seong-Joong Kim, Mrunmay Talegaonkar, Romesh Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu University of Illinois, Urbana-Champaign, IL Dynamic voltage and frequency scaling (DVFS) [1] and burst-mode
ISSCC 2016 Session 23 Wireline I/O
A 32Gb/s Bidirectional 4-Channel 4pJ/b Capacitively Coupled Link in 14nm CMOS for Proximity Communication
Chintan Thakkar, Shreyas Sen, James E. Jaussi, Bryan Casper
Proximity communication offers the convenience of a connector-less high-speed interface using energy-efficient mixed-signal transceivers [1-4]. Such interfaces are attractive for ultra-thin handheld/mobile devices with z
ISSCC 2016 Session 23 Wireline I/O
A 6Gb/s 3-Tap FFE Transmitter and 5-Tap DFE Receiver in 65nm/0.18µm CMOS for NextGeneration 8K Displays
Mohammad Hekmat, Sanquan Song, Nancy Jaffari,
Sabarish Sankaranarayanan, Chaofeng Huang, Minghui Han, Gaurav Malhotra, Jalil Kamali, Amir Amirkhany, Wei Xiong Samsung Semiconductor, San Jose, CA The continuous increase in the resolution, color depth and refresh rate
ISSCC 2016 Session 23 Wireline I/O
A 56Gb/s 300mW Silicon-Photonics Transmitter in 3D-Integrated PIC25G and 55nm BiCMOS Technologies
Enrico Temporiti1, Gabriele Minoia1, Matteo Repossi1,
STMicroelectronics, Pavia, Italy, 2University of Pavia, Pavia, Italy 1 The ever-increasing data center IP traffic, up to 8.6 zettabytes per year by 2018 with nearly 3× growth since 2013 [1], requires power-efficient high
ISSCC 2016 Session 23 Wireline I/O
A Dual 64Gbaud 10kΩ 5% THD Linear Differential Transimpedance Amplifier with Automatic Gain Control in 0.13μm BiCMOS Technology for Optical Fiber Coherent Receivers
Ahmed Awny1, Rajasekhar Nagulapalli1,2, Daniel Micusik1,3,
Schwarz, Munich, Germany, 4 Finisar, Berlin, Germany, 5TU Berlin, Berlin, Germany 1 2 Long-haul optical links are experiencing a transition to coherent techniques because they enable the use of modulation techniques with
ISSCC 2016 Session 23 Wireline I/O
A 30Gb/s 0.8pJ/b 14nm FinFET Receiver Data-Path
Pier Andrea Francese, Matthias Brändli, Christian Menolfi,
Marcel Kossel, Thomas Morf, Lukas Kull, Alessandro Cevrero, Hazar Yueksel, Ilter Oezkaya, Danny Luu, Thomas Toifl IBM Zurich Research Laboratory, Rüshlikon, Switzerland The demand for energy-efficient I/O link transceive
ISSCC 2016 Session 23 Wireline I/O
A 16Gb/s 1 IIR + 1 DT DFE Compensating 28dB Loss with Edge-Based Adaptation Converging in 5μs
Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone
I/O receivers routinely equalize ISI over 10 or more post-cursor UI. IIR DFEs are a low-power technique for canceling long post-cursor ISI tails, and have been demonstrated compensating over 20dB loss at fbit/2 up to 10G
ISSCC 2016 Session 23 Wireline I/O
A 40Gb/s 14mW CMOS Wireline Receiver
Abishek Manian, Behzad Razavi
Reaching a power efficiency of 1mW/Gb/s has proven difficult for wireline transceivers operating at tens of gigabits per second. At 40Gb/s, recent receivers consume from 150mW [1] to 1W [2]. This paper describes a receiv
ISSCC 2016 Session 24 Analog Circuits
A 0.6V 8mW 3D Vision Processor for a Navigation Device for the Visually Impaired
Dongsuk Jeon1,*, Nathan Ickes1, Priyanka Raina1,
devices, such as stereo and time-of-flight (ToF) cameras, measure distances to the observed points and generate a depth image where each pixel represents a distance to the corresponding location. The depth image can be c
ISSCC 2016 Session 24 Analog Circuits
A 2.5GHz 7.7TOPS/W Switched-Capacitor Matrix Multiplier with Co-designed Local Memory in 40nm
Edward H. Lee, S. Simon Wong
Matrix multiplication, enabled by multiply-and-accumulate hardware, is ubiquitous in signal processing, computer graphics, machine learning, and optimization. Many important applications with inherent robustness to reduc
ISSCC 2016 Session 24 Analog Circuits
A 36.8 2b-TOPS/W Self-Calibrating GPS Accelerator Implemented Using Analog Calculation in 65nm LP CMOS
Skylar Skrzyniarz1,2, Laura Fick2, Jinal Shah2, Yejoong Kim2,
Dennis Sylvester2, David Blaauw2, David Fick1, Michael B. Henry1 Isocline, Austin, TX, 2University of Michigan, Ann Arbor, MI 1 Many signal processing applications involve manipulating a large amount of data to generate
ISSCC 2016 Session 25 mm-Wave
A Fully Integrated 0.55THz Near-Field Sensor with a Lateral Resolution down to 8µm in 0.13µm SiGe BiCMOS
Janusz Grzyb1, Bernd Heinemann2, Ullrich R. Pfeiffer1
IHP, Frankfurt, Germany 1 2 Silicon technologies have already been employed in state-of-the-art THz imagers. However, their optical resolution was restricted to millimeters by the diffraction limit [1,2], and THz super-r
ISSCC 2016 Session 25 mm-Wave
A 210-to-305GHz CMOS Receiver for Rotational Spectroscopy
Qian Zhong, Wooyeol Choi, Christopher Miller,
sub-millimeter-wave frequency ranges are used in fast-scan rotational spectroscopy to detect gas molecules and measure their concentrations [1]. This technique can be used for indoor air quality monitoring, detection of
ISSCC 2016 Session 25 mm-Wave
A 40-to-330GHz Synthesizer-Free THz Spectroscope-on-Chip Exploiting Electromagnetic Scattering
Xue Wu, Kaushik Sengupta
The terahertz band (0.3 to 3.0THz) has been found to be spectroscopically rich with many substances possessing strong and unique absorption signatures useful for chemical and biomedical sensing applications [1-4]. Photon
ISSCC 2016 Session 25 mm-Wave
A 0.43K-Noise-Equivalent-ΔT 100GHz Dicke-Free Radiometer with 100% Time Efficiency in 65nm CMOS
A.J. Tang1,2, Yangyho Kim2, Qun Jane Gu1
Jet Propulsion Laboratory, Pasadena, CA 1 2 Silicon based mm-Wave radiometers for sensing, passive imaging, and even biomedical imaging have become an emerging area with many excellent systems demonstrated up to W-band [
ISSCC 2016 Session 25 mm-Wave
A 320GHz Subharmonic-Mixing Coherent Imager in 0.13μm SiGe BiCMOS
Chen Jiang1, Ali Mostajeran1, Ruonan Han2, Mohammad Emadi3,
Crolles, France 1 2 Terahertz imaging has been gaining increasing attention for its emerging applications in security, biomedical and material characterization. Previous works have demonstrated terahertz imagers on silic
ISSCC 2016 Session 26 Wireless
A 5.5mW ADPLL-Based Receiver with HybridLoop Interference Rejection for BLE Application in 65nm CMOS
Hidenori Okuni, Akihide Sai, Tuan Thanh Ta, Satoshi Kondo,
(BLE) have been developed for minimizing the RX power consumption. A PLL-based RX architecture [1] is very attractive to improve the energy efficiency. While the single-channel configuration without multi-bit ADC realize
ISSCC 2016 Session 26 Wireless
An Ultra-Low-Power Receiver Using TransmittedReference and Shifted Limiters for In-Band Interference Resilience
Dawei Ye, Ronan van der Zee, Bram Nauta
The coexistence of more and more wireless standards in the ISM bands increases the design difficulty of interference-robust receivers (RX), especially for Wireless Sensor Nodes because of their Ultra-Low-Power (ULP) budge
ISSCC 2016 Session 26 Wireless
A 1.3nJ/b IEEE 802.11ah Fully Digital Polar Transmitter for IoE Applications
Ao Ba, Yao-Hong Liu, Johan van den Heuvel, Paul Mateman,
Benjamin Busze, Jordy Gloudemans, Peter Vis, Johan Dijkhuis, Christian Bachmann, Guido Dolmans, Kathleen Philips, Harmke de Groot Holst Centre / imec, Eindhoven, The Netherlands This paper presents an ultra-low-power (UL
ISSCC 2016 Session 26 Wireless
A 160-to-960MHz ETSI Class-1-Compliant IoE
Transceiver with 100dB Blocker Rejection, 70dB, ACR and 800pA Standby Current
Niall Kearney1, Charley Billon1, Michael Deeney1, Eric Evans2, Kalim Khan1, Hongxing Li3, Siwen Liang2, Kenneth Mulvaney1, Keith A. O’Donoghue1, Shane O’Mahony1, Philip Quinlan1, Sivanendra Selvanayagam2, Sudarshan Onkar
ISSCC 2016 Session 26 Wireless
A 0.7V 1.5-to-2.3mW GNSS Receiver with 2.5-to-3.8dB NF in 28nm FD-SOI
Ken Yamamoto1, Kenichi Nakano1, Gaku Hidai1, Yuya Kondo1,
Hitoshi Tomiyama1, Hideyuki Takano1, Fumitaka Kondo1, Yusuke Shinohe1, Hidenori Takeuchi1, Nobuhisa Ozawa1, Shingo Harada2, Shinichiro Eto2, Mari Kishikawa3, Daisuke Ide3, Hiroyasu Tagami3, Masayuki Katakura3, Norio Shoj
ISSCC 2016 Session 26 Wireless
A Programmable Receiver Front-End Achieving >17dBm IIP3 at <1.25×BW Frequency Offset
Sameed Hameed1, Neha Sinha1, Mansour Rachid2, Sudhakar Pamarti1
University of California, Los Angeles, CA, Silvus Technologies, Los Angeles, CA 1 2 Recent work on highly selective reconfigurable radios has focused on techniques such as DT analog signal processing [1], N-path filterin
ISSCC 2016 Session 26 Wireless
A 10mm3 Syringe-Implantable Near-Field Radio System on Glass Substrate
Yao Shi, Myungjoon Choi, Ziyun Li, Gyouho Kim, Zhiyoong Foo,
system for ultra-low-power (ULP) healthcare sensor nodes. It is specifically designed for ‘syringe implantation’ which minimizes invasiveness of implantation. Designing a millimeter-scale wireless node for implanted heal
ISSCC 2016 Session 26 Wireless
A 236nW -56.5dBm-Sensitivity Bluetooth Low-Energy Wakeup Receiver with Energy Harvesting in 65nm CMOS
Nathan E. Roberts1, Kyle Craig1, Aatmesh Shrivastava1,
Stuart N. Wooters1, Yousef Shakhsheer1, Benton H. Calhoun1, David D. Wentzloff2 PsiKick, Charlottesville, VA, 2PsiKick, Ann Arbor, MI 1 Batteryless operation and ultra-low-power (ULP) wireless communication will be two k
ISSCC 2016 Session 26 Wireless
A 0.038mm2 SAW-less Multiband Transceiver Using an N-Path SC Gain Loop
Gengzhen Qi1, Pui-In Mak1, Rui P. Martins1,2
Instituto Superior Tecnico, Lisbon, Portugal 1 2 N-path filtering has been intensely rekindled as a replacement of costly SAW filters, making possible of multiband blocker-tolerant receivers (RXs) at small area and power
ISSCC 2016 Session 27 Data Converters
A 12b 2GS/s Dual-Rate Hybrid DAC with Pulsed Timing-Error Pre-Distortion and In-Band Noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS
Shiyu Su, Mike Shuo-Wei Chen
A dual-rate hybrid DAC is proposed in [1] that shows a path toward high speed/linearity in scaled technology. In this hybrid architecture, the resolution of the DAC is achieved through an oversampled LSB path, while its
ISSCC 2016 Session 27 Data Converters
An Oversampling SAR ADC with DAC Mismatch Error Shaping Achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS
Yun-Shiang Shu, Liang-Ting Kuo, Tien-Yu Lo
The successive-approximation-register (SAR) architecture is well-known for its high power efficiency in medium-resolution A/D conversions. Together with time interleaving, it can challenge the regime of flash ADCs in hig
ISSCC 2016 Session 27 Data Converters
Area-Efficient 1GS/s 6b SAR ADC with ChargeInjection-Cell-Based DAC
Kyojin D. Choo, John Bell, Michael P Flynn
To support growing data bandwidths, high-speed moderate-resolution ADCs have become vital for high-speed serial links. Interleaved SAR ADCs achieve high sampling speeds and good energy efficiency. However a challenge is
ISSCC 2016 Session 27 Data Converters
A 0.35mW 12b 100MS/s SAR-Assisted Digital Slope ADC in 28nm CMOS Chun-Cheng Liu
MediaTek, Hsinchu, Taiwan
In recent years, the operation speed of SAR ADCs has improved with the scaling of CMOS technology. SAR ADCs achieve a few hundreds of MS/s with 8-to-10b resolution. The SNR of high-speed SAR ADCs is mainly dominated by c
ISSCC 2016 Session 27 Data Converters
A 4GS/s Time-Interleaved RF ADC in 65nm CMOS with 4GHz Input Bandwidth
Matt Straayer1, Jim Bales2, Dwight Birdsall2, Denis Daly1,
Phillip Elliott2, Bill Foley1, Roy Mason2, Vikas Singh3, Xuejin Wang2 Maxim Integrated Products, North Chelmsford, MA, Maxim Integrated Products, Fort Collins, CO, 3 Maxim Integrated Products, San Jose, CA 1 2 The perfor
ISSCC 2016 Session 27 Data Converters
A 4GS/s 13b Pipelined ADC with Capacitor and Amplifier Sharing in 16nm CMOS
Jiangfeng Wu1,2, Acer Chou1, Tianwei Li1, Rong Wu1, Tao Wang1,
Giuseppe Cusmai1, Sha-Ting Lin3, Cheng-Hsun Yang3, Gregory Unruh1, Sunny Raj Dommaraju1, Mo M. Zhang1, Po Tang Yang3, Wei-Ting Lin3, Xi Chen1, Dongsoo Koh1, Qingqi Dou1, H. Mohan Geddada1, Juo-Jung Hung1, Massimo Brandol
ISSCC 2016 Session 27 Data Converters
A 10b 2.6GS/s Time-Interleaved SAR ADC with Background Timing-Skew Calibration
Chin-Yu Lin, Yen-Hsin Wei, Tai-Cheng Lee
Recent radio architectures, such as WiGig and 5G, require ADCs with bandwidth beyond 1GHz and ENOB of 6-to-8b while retaining excellent power efficiency for long battery life. Therefore, many time-interleaved SAR ADCs ar
ISSCC 2016 Session 27 Data Converters
A 0.076mm2 12b 26.5mW 600MS/s 4×-Interleaved Subranging SAR-ΔΣ ADC with On-Chip Buffer in 28nm CMOS switch, is parasitic sensitive. Scaling of the LSB capacitance is therefore dictated by the parasitic capacitance of a minimum size switch instead of kT/C noise requirements. In deep-submicron technologies, this usually leads to a significantly larger core area with respect to a CR-DAC.
Alessandro Venca, Nicola Ghittori, Alessandro Bosi, Claudio Nani, To exploit the CS-DAC area advantage in the reference
competitive core area a segmented SAR-DAC architecture is adopted using a CSDAC for the 4 MSBs and a CR-DAC for the remaining 6 LSBs (Fig. 27.8.2). The parasitic insensitive 6 LSBs can be scaled down as in a conventional
ISSCC 2016 Session 28 Medical & Bio
A Handheld 50pM-Sensitivity Micro-NMR CMOS Platform with B-Field Stabilization for Multi-Type Biological/Chemical Assays
Ka-Meng Lei1, Hadi Heidari2,3, Pui-In Mak1, Man-Kay Law1,
Franco Maloberti2, Rui P. Martins1,4 University of Macau, Macau, China, University of Pavia, Pavia, Italy, 3 University of Glasgow, Glasgow, United Kingdom, 4 Instituto Superior Tecnico, Lisbon, Portugal 1 2 Point-of-use
ISSCC 2016 Session 28 Medical & Bio
A 14GHz Battery-Operated Point-of-Care ESR Spectrometer Based on a 0.13µm CMOS ASIC
Jonas Handwerker, Benedikt Schlecker, Ulrich Wachter,
spatial distribution, and even dynamics of paramagnetic species, electron spin resonance (ESR) spectroscopy is one of the most powerful analytical techniques in modern life sciences. Recently, the method has gained signi
ISSCC 2016 Session 28 Medical & Bio
CMOS Biosensor IC Focusing on Dielectric Relaxations of Biological Water with 120GHz and 60GHz Oscillator Arrays
Takeshi Mitsunaka1, Nobuyuki Ashida1, Akira Saito1,
are reduced to 0.07GHz (resp. 0.03GHz) if we exclude the 52 elements (resp. 44 elements) on the periphery that exhibit larger deviations due to the anisotropy of the layout. A selected 120GHz (resp. 60GHz) element draws
ISSCC 2016 Session 28 Medical & Bio
A Battery-Powered Efficient Multi-Sensor
Acquisition System with Simultaneous ECG, BIO-Z, GSR, and PPG
Mario Konijnenburg1, Stefano Stanzione1, Long Yan2, Dong-Woo Jee2, Julia Pettine1, Roland van Wegberg1, Hyejung Kim2, Chris van Liempd1, Ram Fish3, James Schluessler3, Harmke de Groot1, Chris van Hoof1,2, Refet Firat Yaz
ISSCC 2016 Session 28 Medical & Bio
A 0.6V 0.015mm2 Time-Based Biomedical Readout for Ambulatory Applications in 40nm CMOS
Rachit Mohan1,2, Samira Zaliasl3, Georges Gielen1,2,
applications in personal healthcare require sensor SoCs with low area, low power and a high dynamic range. Design in small-scale technologies can reduce the power and area of digital processing. However, due to the accom
ISSCC 2016 Session 28 Medical & Bio
A ±50mV Linear-Input-Range VCO-Based NeuralRecording Front-End with Digital Nonlinearity Correction
Wenlong Jiang1, Vahagn Hokhikyan1, Hariprasad Chandrakumar1,
tool for understanding the brain and driving the progress in neuroscience research and therapy. The local field potential (LFP) signals, which span from 3Hz to about 200Hz, serve as indicators of various neurological beh
ISSCC 2016 Session 28 Medical & Bio
CMOS Monolithic Airborne-Particulate-Matter Detector Based on 32 Capacitive Sensors with a Resolution of 65zF rms
Pietro Ciccarella, Marco Carminati, Marco Sampietro, Giorgio Ferrari
matter (PM) is well known [1]. Although optical and gravimetric instruments are available to detect PM, they lack portability, have poor potential for miniaturization, and are not low cost. Instead, a better spatio-tempo
ISSCC 2016 Session 3 Wireline I/O
A 25Gb/s ADC-Based Serial Line Receiver in 32nm CMOS SOI
Sergey Rylov1, Troy Beukema1, Zeynep Toprak-Deniz1,
Thomas Toifl2, Yong Liu3, Ankur Agrawal1, Peter Buchmann2, Alexander Rylyakov4, Michael Beakes1, Benjamin Parker1, Mounir Meghelli1 IBM T. J. Watson Reseach Center, Yorktown Heights, NY, IBM Zurich Research Laboratory, R
ISSCC 2016 Session 3 Wireline I/O
A 320mW 32Gb/s 8b ADC-Based PAM-4 Analog Front-End with Programmable Gain Control and Analog Peaking in 28nm CMOS
Delong Cui1, Heng Zhang1, Nick Huang1,2, Ali Nazemi1, Burak Catli1,
introduced in recent years for next generation wireline communication systems for more efficient use of the available link bandwidth. High-speed ADCs with digital signal processing (DSP) can provide robust performance fo
ISSCC 2016 Session 3 Wireline I/O
A 25Gb/s Multistandard Serial Link Transceiver for 50dB-Loss Copper Cable in 28nm CMOS
Takayasu Norimatsu1, Takashi Kawamoto1, Kenji Kogo1,
Naohiro Kohmu1, Fumio Yuki1, Norio Nakajima2, Takashi Muto2, Junya Nasu2, Takemasa Komori2, Hideki Koba2, Tatsunori Usugi2, Tomofumi Hokari2, Tsuneo Kawamata2, Yuichi Ito2, Seiichi Umai2, Masatoshi Tsuge2, Takeo Yamashit
ISSCC 2016 Session 3 Wireline I/O
A 40/50/100Gb/s PAM-4 Ethernet Transceiver in 28nm CMOS
Karthik Gopalakrishnan1, Alan Ren1, Amber Tan1, Arash Farhood1,
Arun Tiruvur1, Belal Helal1, Chang-Feng Loi2, Chris Jiang1, Halil Cirit1, Irene Quek2, Jamal Riani1, James Gorecki1, Jennifer Wu1, Jorge Pernillo1, Lawrence Tse1, Michael Le3, Mohammad Ranjbar1, Pui-Shan Wong1, Pulkit Kh
ISSCC 2016 Session 3 Wireline I/O
A 56Gb/s NRZ-Electrical 247mW/lane Serial-Link Transceiver in 28nm CMOS
Takayuki Shibasaki1, Takumi Danjo1, Yuuki Ogata1,
Yasufumi Sakai1, Hiroki Miyaoka2, Futoshi Terasawa2, Masahiro Kudo2, Hideki Kano2, Atsushi Matsuda2, Shigeaki Kawai2, Tomoyuki Arai2, Hirohito Higashi2, Naoaki Naka2, Hisakatsu Yamaguchi1, Toshihiko Mori1, Yoichi Koyanag