ISSCC 2017

2017

208 篇论文 · Wireless (27) · Digital Processors (24) · Wireline I/O (24) · Memory (17) · Power Management (15)

ISSCC 2017 Session 29 Wireline I/O
A 2.5GHz Injection-Locked ADPLL with 197fsrms Integrated Jitter and -65dBc Reference Spur Using Time-Division Dual Calibration
Sungwoo Kim1, Han-Gon Ko1, Sung-Yong Cho1, Jinhyung Lee1,
7.3 shows the implemented schematic of the TDDC. The ILO is based on a pseudo-differential 4-stage ring oscillator, whose frequency is controlled by the 10b FCW. The frequency resolution is 100kHz/LSB. The FEPMD controls
Soyeong Shin1, Min-Seong Choo1, Hankyu Chi2, Deog-Kyoon Jeong1 Seoul N
ISSCC 2017 Session 3 Digital Processors
POWER9TM: A Processor Family Optimized for Cognitive Computing with 25Gb/s Accelerator Links and 16Gb/s PCIe Gen4
Christopher Gonzalez1, Eric Fluhr2, Daniel Dreps2, David Hogenmiller2,
Rahul Rao3, Jose Paredes2, Michael Floyd2, Michael Sperling4, Ryan Kruse2, Vinod Ramadurai2, Ryan Nett2, Saiful Islam2, Juergen Pille5, Donald Plass4 IBM, Yorktown Heights, NY IBM, Austin, TX 3 IBM, Bangalore, India 4 IB
ISSCC 2017 Session 3 Digital Processors
Zen: A Next-Generation High-Performance x86 Core
Teja Singh1, Sundar Rangarajan1, Deepesh John1, Carson Henrion2,
Shane Southard1, Hugh McIntyre3, Amy Novak1, Stephen Kosonocky2, Ravi Jotwani1, Alex Schaefer1, Edward Chang2, Joshua Bell1, Michael Co1 AMD, Austin, TX AMD, Fort Collins, CO 3 AMD, Sunnyvale, CA 1 2 Codenamed “Zen”, AMD
ISSCC 2017 Session 3 Digital Processors
A 14nm 1GHz FPGA with 2.5D Transceiver Integration
David Greenhill1, Ron Ho1, David Lewis2, Herman Schmit1,
Kok Hong Chan1, Andy Tong1, Sean Atsatt1, Dana How1, Peter McElheny1, Keith Duwel1, Jeffrey Schulz1, Darren Faulkner3, Gopal Iyer1, George Chen1, Hee Kong Phoon4, Han Wooi Lim4, Wei-Yee Koay4, Ty Garibay3 Intel, San Jose
ISSCC 2017 Session 3 Digital Processors
A 10nm FinFET 2.8GHz Tri-Gear Deca-Core CPU Complex with Optimized Power-Delivery Network for Mobile SoC Performance
Hugh Mair1, Ericbill Wang2, Alice Wang2, Ping Kao2, Yuwen Tsai2,
Sumanth Gururajarao1, Rolf Lagerquist1, Jin Son1, Gordon Gammie1, Gordon Lin2, Achuta Thippana1, Kent Li1, Manzur Rahman1, Wuan Kuo2, David Yen2, Yi-Chang Zhuang2, Ue Fu2, Hung-Wei Wang2, Mark Peng3, Cheng-Yuh Wu2, Taner
ISSCC 2017 Session 3 Digital Processors
A 40nm Flash Microcontroller with 0.80μs FieldOriented-Control Intelligent Motor Timer and Functional Safety System for Next-Generation EV/HEV
Hayato Kimura1, Hideyuki Noda1, Hisaaki Watanabe1, Takashi Higuchi1,
Ryosaku Kobayashi2, Masayuki Utsuno1, Fumitake Takami1, Sugako Otani1, Masayuki Ito1, Yasuhisa Shimazaki1, Naoki Yada1, Hiroyuki Kondo1 Renesas Electronics, Tokyo, Japan Renesas System Design, Tokyo, Japan 1 2 Electric V
ISSCC 2017 Session 3 Digital Processors
A 60pJ/b 300Mb/s 128×8 Massive MIMO Precoder-Detector in 28nm FD-SOI
Hemanth Prabhu, Joachim Neves Rodrigues, Liang Liu, Ove Edfors
Further exploitation of the spatial domain, as in Massive MIMO (MaMi) systems, is imperative to meet future communication requirements [1]. Up-scaling of conventional 4×4 small-scale MIMO implementations to MaMi is prohi
Lund University, Lund, Sweden
ISSCC 2017 Session 3 Digital Processors
A 1920×1080 30fps 2.3TOPS/W Stereo-Depth Processor for Robust Autonomous Navigation
Ziyun Li, Qing Dong, Mehdi Saligane, Benjamin Kempke, Shijia Yang,
realizing autonomous navigation on micro-aerial vehicles (MAVs). The state-of-the-art semi-global matching (SGM) algorithm has become favored for its high accuracy. In particular, it effectively handles low texture regio
Zhengya Zhang, Ronald Dreslinski, Dennis Sylvester, David Blaauw, Hun
ISSCC 2017 Session 4 Image Sensors
A 640×480 Dynamic Vision Sensor with a 9μm Pixel and 300Meps Address-Event Representation
Bongki Son1, Yunjae Suh1, Sungho Kim1, Heejae Jung1, Jun-Seok Kim1,
Changwoo Shin1, Keunju Park1, Kyoobin Lee1, Jinman Park1, Jooyeon Woo1, Yohan Roh1, Hyunku Lee1, Yibing Wang2, Ilia Ovsiannikov2, Hyunsurk Ryu1 Samsung Advanced Institute of Technology, Suwon, Korea Samsung Electronics,
ISSCC 2017 Session 4 Image Sensors
A Fully Integrated CMOS Fluorescence Biochip for Multiplex Polymerase Chain-Reaction (PCR) Processes
Arjang Hassibi, Rituraj Singh, Arun Manickam, Ruma Sinha,
Bob Kuimelis, Sara Bolouki, Pejman Naraghi-Arani, Kirsten Johnson, Mark McDermott, Nicholas Wood, Piyush Savalia, Nader Gamini InSilixa, Sunnyvale, CA Integration and miniaturization of bio-molecular detection systems in
ISSCC 2017 Session 4 Image Sensors
A Programmable Sub-Nanosecond Time-Gated 4-Tap Lock-In Pixel CMOS Image Sensor for Real-Time Fluorescence Lifetime Imaging Microscopy
Min-Woong Seo, Yuya Shirakawa, Yuriko Masuda, Yoshimasa Kawata,
effective methods in life science and medicine. Among others, fluorescence lifetime imaging microscopy (FLIM) is one of the representative measurement techniques for biomedical applications. Recently, advanced all-solid-
Keiichiro Kagawa, Keita Yasutomi, Shoji Kawahito Shizuoka University,
ISSCC 2017 Session 4 Image Sensors
A Sub-nW 80mlx-to-1.26Mlx Self-Referencing Light-to-Digital Converter with AlGaAs Photodiode
Wootaek Lim, Dennis Sylvester, David Blaauw
Wearable sensors are increasingly common and continue to grow more diverse in their sensing modalities, ranging from glucose to heart rate monitoring. One compelling sensing modality for wearable sensors is cumulative li
University of Michigan, Ann Arbor, MI
ISSCC 2017 Session 4 Image Sensors
A 1.8e-rms Temporal Noise Over 110dB Dynamic Range 3.4μm Pixel Pitch Global Shutter CMOS Image Sensor
with Dual-Gain Amplifiers, SS-ADC and MultipleAccumulation Shutter
Masahiro Kobayashi, Yusuke Onuki, Kazunari Kawabata, Hiroshi Sekine, Toshiki Tsuboi, Yasushi Matsuno, Hidekazu Takahashi, Toru Koizumi, Katsuhito Sakurai, Hiroshi Yuzurihara, Shunsuke Inoue, Takeshi Ichikawa Canon, Kanag
ISSCC 2017 Session 4 Image Sensors
A 1/2.3inch 20Mpixel 3-Layer Stacked CMOS Image Sensor with DRAM
Tsutomu Haruta1, Tsutomu Nakajima1, Jun Hashizume1,
Taku Umebayashi1, Hiroshi Takahashi1, Kazuo Taniguchi1, Masami Kuroda1, Hiroshi Sumihiro1, Koji Enoki1, Takatsugu Yamasaki2, Katsuya Ikezawa1, Atsushi Kitahara1, Masao Zen1, Masafumi Oyama1, Hiroki Koga1, Hidenobu Tsugaw
ISSCC 2017 Session 4 Image Sensors
A 2.1Mpixel Organic-Film Stacked RGB-IR Image Sensor with Electrically Controllable IR Sensitivity
Shin'ichi Machida, Sanshiro Shishido, Takeyoshi Tokuhara,
Masaaki Yanagida, Takayoshi Yamada, Masumi Izuchi, Yoshiaki Sato, Yasuo Miyake, Manabu Nakata, Masashi Murakami, Mitsuru Harada, Yasunori Inoue Panasonic, Osaka, Japan The use of infrared (IR) imaging to view scenes othe
ISSCC 2017 Session 4 Image Sensors
A 0.44e-rms Read-Noise 32fps 0.5Mpixel HighSensitivity RG-Less-Pixel CMOS Image Sensor Using Bootstrapping Reset
Min-Woong Seo1, Tongxi Wang1, Sung-Wook Jun2, Tomoyuki Akahori2,
noise level, particularly, deep sub-electron read noise (less than 0.5e-rms), have been reported. Such an ultra-low noise level is realized with a reduced floating diffusion (FD) node capacitance for attaining the high p
Shoji Kawahito1,2 Shizuoka University, Hamamatsu, Japan 2 Brookman Tec
ISSCC 2017 Session 4 Image Sensors
A 1ms High-Speed Vision Chip with 3D-Stacked 140GOPS Column-Parallel PEs for Spatio-Temporal Image Processing
Tomohiro Yamazaki1, Hironobu Katayama1, Shuji Uehara1, Atsushi Nose1,
Masatsugu Kobayashi1, Sayaka Shida1, Masaki Odahara2, Kenichi Takamiya2, Yasuaki Hisamatsu2, Shizunori Matsumoto2, Leo Miyashita3, Yoshihiro Watanabe3, Takashi Izawa1, Yoshinori Muramatsu1, Masatoshi Ishikawa3 Sony Semic
ISSCC 2017 Session 5 Analog Circuits
A 5×80W 0.004% THD+N Automotive Multiphase Class-D Audio Amplifier with Integrated Low-Latency ΔΣ ADCs for Digitized Feedback after the Output Filter problem, a special low-latency ΔΣ ADC (LLADC) is proposed with lowpass filtering DACs (FIRDACs) in its feedback path. By giving the digital filter the same transfer function as the FIRDAC, the overall signal transfer function (STF) becomes approximately flat with little phase shift, while HF quantization noise is reduced.
Fred Mostert1, Daniel Schinkel1,2, Wouter Groothedde2, Lucien Breems3,
Remko van Heeswijk1, Marto-Jan Koerts1, Eric van Iersel1, Daniel Groeneveld2, Gertjan van Holland1, Patrick Zeelen1, Derk-Jan Hissink1, Martin Pos1, Paul Wielage1, Fre Jorritsma1, Marc Klein Middelink1 The ADC core (Fig.
ISSCC 2017 Session 5 Analog Circuits
A 1A LDO Regulator Driven by a 0.0013mm2 Class-D Controller
Weiwei Xu, Prasanna Upadhyaya, Xiaoyue Wang, Randy Tsang, Li Lin
Marvell, Santa Clara, CA A low-dropout (LDO) regulator generates a DC supply for electronic systems. Today’s high-throughput wireless system-on-chips (SOCs) require large dynamic range of supply current, which demands a
ISSCC 2017 Session 5 Analog Circuits
A 65nm Inverter-Based Low-Dropout Regulator with Rail-to-Rail Regulation and over -20dB PSR at 0.2V Lowest Supply Voltage
Fan Yang, Philip K. T. Mok
Ultra-low-voltage operation is highly demanded in a system that adopts the DVFS scheme, e.g., a portable device that sustains days-long standby with a tiny battery. Such a system usually embeds modules that have specific
Hong Kong University of Science and Technology, Hong Kong, China
ISSCC 2017 Session 5 Analog Circuits
An 8Ω 10W 91%-Power-Efficiency 0.0023%-THD+N Multi-Level Class-D Audio Amplifier with Folded PWM
Ji-Hun Lee, Jun-Suk Bang, Ki-Duk Kim, Hui-Dong Gwon, Sang-Hui Park,
Yeunhee Huh, Kye-Seok Yoon, Jong-Beom Baek, Yong-Min Ju, Gibbeum Lee, Homin Park, Hyeon-Min Bae, Gyu-Hyeong Cho KAIST, Daejeon, Korea As the portable device market tries to enhance user experience, high-power audio syste
ISSCC 2017 Session 5 Analog Circuits
A 95μW 24MHz Digitally Controlled Crystal Oscillator for IoT Applications with 36nJ Start-Up Energy and >13× Start-Up Time Reduction Using A FullyAutonomous Dynamically-Adjusted Load
Ming Ding, Yao-Hong Liu, Yan Zhang, Chuang Lu, Peng Zhang,
g., Bluetooth Low Energy, BLE) rely on heavily duty-cycling the wireless transceivers to reduce the overall system power consumption [1]. This requires swift start-up behavior of the transceiver. The crystal oscillator (
Benjamin Busze, Christian Bachmann, Kathleen Philips Holst Centre / im
ISSCC 2017 Session 5 Analog Circuits
Frequency-Locked-Loop Ring Oscillator with 3ns Peak-to-Peak Accumulated Jitter in 1ms Time Window for High-Resolution Frequency Counting
Karthik Pappu, George Pieter Reitsma, Sumant Bapat
Many sensing applications require a high-resolution frequency measurement. These applications include measurement of pressure, acceleration and eddycurrent sensing. In these applications the sensor is part of an oscillat
Texas Instruments, Santa Clara, CA
ISSCC 2017 Session 5 Analog Circuits
A Quadrature Relaxation Oscillator with a ProcessInduced Frequency-Error Compensation Loop
Jahyun Koo1, Kyoung-Sik Moon2, Byungsub Kim1, Hong-June Park1, Jae-Yoon Sim1
wearable and implantable technologies, there has been growing demand on development of key enabling circuits for ultra-low-power sensor interface SoCs. As a reference-frequency generation block for clock management of th
Pohang University of Science and Technology, Pohang, Korea Research In
ISSCC 2017 Session 5 Analog Circuits
A 0.68nW/kHz Supply-Independent Relaxation Oscillator with ±0.49%/V and 96ppm/°C Stability
Anand Savanth1,2, James Myers1, Alex Weddell2, David Flynn1,2, Bashir Al-Hashimi2
are attractive for integrated clock sources compared to LC and ring oscillators (RO), as LC oscillators pose integration challenges and RO designs have limited voltage and temperature (V-T) stability. RxOs generate a clo
ARM, Cambridge, United Kingdom University of Southampton, Southampton,
ISSCC 2017 Session 5 Analog Circuits
A 19nV/√Hz-Noise 2μV-Offset 75μA Low-Drift Capacitive-Gain Amplifier with Switched-Capacitor ADC Driving Capability
Hanqing Wang1, Gerard Mora-Puchalt2, Colin Lyden3, Roberto Maurino4, Christian Birk3
(CGA) with amplifier common-mode sampling (CMS) and switched-capacitor driving capability, compatible with many conventional switched-capacitor ADC inputs (SCAI) such as delta-sigma modulators or SAR ADCs. CGAs are popul
Analog Devices, Beijing, China Analog Devices, Valencia, Spain 3 Analo
ISSCC 2017 Session 5 Analog Circuits
A 9.3nW All-in-One Bandgap Voltage and Current Reference Circuit
Youngwoo Ji, Cheonhoo Jeon, Hyunwoo Son, Byungsub Kim,
have presented challenges in ULP implementation of reference circuits while keeping traditional requirements of stable performance. For voltage reference circuits, as an essential block in SoCs to generate various intern
Hong-June Park, Jae-Yoon Sim Pohang University of Science and Technolo
ISSCC 2017 Session 5 Analog Circuits
An 18.75μW Dynamic-Distributing-Bias Temperature Sensor with 0.87°C(3σ) Untrimmed Inaccuracy and 0.00946mm2 Area
Ying-Chih Hsu1, Chia-Liang Tai1, Mei-Chen Chuang1, Alan Roth2, Eric Soenen2
The overall system mismatch will be averaged out through the lowpass digital counter, and the stable output codes can be obtained. The measured differences between the cases with and without the DEM are shown in Fig. 5.9
TSMC, Hsinchu, Taiwan TSMC, Austin, TX 1 to be 16 times the clock cycl
ISSCC 2017 Session 6 Wireline I/O
A 56Gb/s PAM-4/NRZ Transceiver in 40nm CMOS
Pen-Jui Peng, Jeng-Feng Li, Li-Yang Chen, Jri Lee
Ultra-high speed data links such as 400GbE continuously push transceivers to achieve better performance and lower power consumption. This paper presents a highly parallelized TRX at 56Gb/s with integrated serializer/dese
National Taiwan University, Taipei, Taiwan
ISSCC 2017 Session 6 Wireline I/O
A 60Gb/s 288mW NRZ Transceiver with Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65nm CMOS Technology
Jaeduk Han1, Yue Lu2, Nicholas Sutardja1, Elad Alon1
Qualcomm Atheros, San Jose, CA 1 2 The demand for ultra-high speed transceivers continues to explode, and while the data-rate for high-speed I/O standards has increased accordingly, the historically constant or even decr
University of California, Berkeley, CA
ISSCC 2017 Session 6 Wireline I/O
A 40-to-56Gb/s PAM-4 Receiver with 10-Tap Direct Decision-Feedback Equalization in 16nm FinFET
Jay Im1, Dave Freitas1, Arianne Roldan2, Ronan Casey3, Stanley Chen1,
Adam Chou1, Tim Cronin1, Kevin Geary3, Scott McLeod1, Lei Zhou1, Ian Zhuang1, Jaeduk Han4, Sen Lin4, Parag Upadhyaya1, Geoff Zhang1, Yohan Frans1, Ken Chang1 Xilinx, San Jose, CA Xilinx, Singapore, Singapore 3 Xilinx, Co
ISSCC 2017 Session 6 Wireline I/O
A 64Gb/s PAM-4 Transmitter with 4-Tap FFE and 2.26pJ/b Energy Efficiency in 28nm CMOS FDSOI
Giovanni Steffan1, Emanuele Depaoli1, Enrico Monaco1, Nicolo Sabatino1,
Walter Audoglio1, Augusto Andrea Rossi1, Simone Erba1, Matteo Bassi2, Andrea Mazzanti2 STMicroelectronics, Pavia, Italy University of Pavia, Pavia, Italy 1 2 Electrical link migration requires serial interfaces to operat
ISSCC 2017 Session 6 Wireline I/O
A 1.8pJ/b 56Gb/s PAM-4 Transmitter with Fractionally Spaced FFE in 14nm CMOS
Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli
As data rates in electrical links rise to 56Gb/s, standards are gravitating towards PAM-4 modulation to achieve higher spectral efficiency. Such approaches are not without drawbacks, as PAM-4 signaling results in reduced
IBM T. J. Watson Research Center, Yorktown Heights, NY
ISSCC 2017 Session 6 Wireline I/O
A 22.5-to-32Gb/s 3.2pJ/b Referenceless Baud-Rate Digital CDR with DFE and CTLE in 28nm CMOS
Wahid Rahman1, Danny Yoo1, Joshua Liang1, Ali Sheikholeslami1,
circuits (CDRs) are becoming more prevalent in high-speed receiver designs as they offer lower power consumption by sampling the received data only once per UI [1,2]. This reduces the number of front-end comparators and
Hirotaka Tamura2, Takayuki Shibasaki2, Hisakatsu Yamaguchi2 University
ISSCC 2017 Session 6 Wireline I/O
A 28Gb/s Digital CDR with Adaptive Loop Gain for Optimum Jitter Tolerance
Joshua Liang1, Ali Sheikholeslami1, Hirotaka Tamura2, Yuuki Ogata2, Hisakatsu Yamaguchi2
(CDR) circuits becomes increasingly important in maintaining low bit error rates (BER) in wireline links. Digital CDRs are popular in part for their robustness, but their use of bang-bang phase detectors (BB-PD) makes th
University of Toronto, Toronto, Canada Fujitsu Laboratories, Kawasaki,
ISSCC 2017 Session 7 Wireless
An 802.11ac Dual-Band Reconfigurable Transceiver Supporting up to Four VHT80 Spatial Streams with 116fsrms-Jitter Frequency Synthesizer and Integrated LNA/PA Delivering 256QAM 19dBm per Stream Achieving 1.733Gb/s PHY Rate
Tsung-Ming Chen1, Yi Lu1, Pang-Ning Chen1, Yu-Hsien Chang1,
Ming-Chung Liu1, Po-Yu Chang1, Chia-Jen Liang1, Yi-Chu Chen1, Hsi-Liang Lu1, Jian-Yu Ding1, Chin-Chung Wang1, Yu-Li Hsueh1, Jen-Che Tsai1, Min-Shun Hsu1, Yuan-Hung Chung1, George Chien2 MediaTek, Hsinchu, Taiwan; 2MediaT
ISSCC 2017 Session 7 Wireless
A 28GHz 32-Element Phased-Array Transceiver IC with Concurrent Dual Polarized Beams and 1.4 Degree Beam-Steering Resolution for 5G Communication
Bodhisatwa Sadhu1, Yahya Tousi1, Joakim Hallin2, Stefan Sahl3,
Scott Reynolds1, Örjan Renström3, Kristoffer Sjögren2, Olov Haapalahti3, Nadav Mazor4, Bo Bokinge3, Gustaf Weibull2, Håkan Bengtsson3, Anders Carlinger3, Eric Westesson5, Jan-Erik Thillberg3, Leonard Rexberg3, Mark Yeck1
ISSCC 2017 Session 7 Wireless
A 40nm Low-Power Transceiver for LTE-A Carrier Aggregation
Chinq-Shiun Chiu1, Shih-Chieh Yen1, Chi-Yao Yu1, Tzung-Han Wu1,
Chung-Yun Chou1, Sheng-Che Tseng1, Chih-Hsien Shen1, Yu-Tsung Lu1, Hsinhung Chen1, Song-Yu Yang1, Yen-Tso Chen1, Guang-Kaai Dehng1, Yangjian Chen2, Christophe Beghein2, Dimitris Nalbantis2, Manel Collados2, Bernard Tenbr
ISSCC 2017 Session 7 Wireless
A 915MHz Asymmetric Radio Using Q-Enhanced Amplifier for a Fully Integrated 3×3×3mm3 Wireless Sensor Node with 20m Non-Line-of-Sight Communication
Li-Xuan Chuo1, Yao Shi1, Zhihong Luo1, Nikolaos Chiotellis1,
Zhiyoong Foo1,2, Gyouho Kim1,2, Yejoong Kim1,2, Anthony Grbic1, David Wentzloff1, Hun-Seok Kim1, David Blaauw1 University of Michigan, Ann Arbor, MI CubeWorks, Ann Arbor, MI 1 2 Enabling long range (>10m) wireless commun
ISSCC 2017 Session 7 Wireless
A TCXO-Less 100Hz-Minimum-Bandwidth Transceiver for Ultra-Narrow-Band Sub-GHz IoT Cellular Networks
David Lachartre1, François Dehmas1, Carolynn Bernier1,
Christophe Fourtet2, Laurent Ouvry1, Florent Lepin1, Eric Mercier1, Steve Hamard2, Lionel Zirphile2, Sébastien Thuries1, Fabrice Chaix1 CEA-LETI-MINATEC, Grenoble, France Sigfox, Labège, France 1 2 Ultra-narrow-band (UNB
ISSCC 2017 Session 7 Wireless
A +8dBm BLE/BT Transceiver with Automatically Calibrated Integrated RF Bandpass Filter and -58dBc TX HD2
Wei Yang, De Yong Hu, Chun Kit Lam, Ji Qing Cui, Lip Kai Soh,
Internet-of-Things (IoT) applications, highly integrated ultra-low-power (ULP) RF transceivers are essential, and numerous solutions have been proposed [3,4]. These architectures address the less-stringent Bluetooth Low-
De Cheng Song, Xiao Wei Zhong, Hon Cheong Hor, Chee Lee Heng MediaTek,
ISSCC 2017 Session 7 Wireless
A 118mW 23.3GS/s Dual-Band 7.3GHz and 8.7GHz Impulse-Based Direct RF Sampling Radar SoC in 55nm CMOS
Nikolaj Andersen1, Kristian Granhaug1, Jørgen Andreas Michaelsen1,
Sumit Bagga1, Håkon A. Hjortland1, Mats Risopatron Knutsen1, Tor Sverre Lande2, Dag T. Wisland1,2 Novelda AS, Oslo, Norway University of Oslo, Oslo, Norway 1 2 Radar sensors find use in a wide range of applications [1–4]
ISSCC 2017 Session 8 Digital Circuits
Improved Power-Side-Channel-Attack Resistance of an AES-128 Core via a Security-Aware Integrated Buck Voltage Regulator
Monodeep Kar1, Arvind Singh1, Sanu Mathew2, Anand Rajan2, Vivek De2, Saibal Mukhopadhyay1
g. Differential Power Analysis (DPA) and Correlation Power Analysis (CPA), are major threats to the security of crypto engines in SoC platforms. Circuit-level SCA countermeasures to achieve dataindependent supply current
Georgia Institute of Technology, Atlanta, GA Intel, Hillsboro, OR 1 2
ISSCC 2017 Session 8 Digital Circuits
8Mb/s 28Mb/mJ Robust True-Random-Number Generator in 65nm CMOS Based on Differential Ring Oscillator with Feedback Resistors
Eunhwan Kim, Minah Lee, Jae-Joon Kim
On-chip true random number generators (TRNG) have been gaining attention as an important component for building secure systems [1]. CMOS TRNGs typically exploit device-level noise, such as thermal or flicker noise to gen
Pohang University of Science and Technology, Pohang, Korea
ISSCC 2017 Session 8 Digital Circuits
A 553F2 2-Transistor Amplifier-Based Physically Unclonable Function (PUF) with 1.67% Native Instability
Kaiyuan Yang, Qing Dong, David Blaauw, Dennis Sylvester
Physically Unclonable Functions (PUFs) are among the most promising security primitives for low cost solutions of key storage, chip authentication, and supply chain protection. Two types of PUFs exist in literature [1-6]
University of Michigan, Ann Arbor, MI
ISSCC 2017 Session 8 Digital Circuits
A 2.5ps 0.8-to-3.2GHz Bang-Bang Phase- and Frequency-Detector-Based All-Digital PLL with Noise Self-Adjustment
Taekwang Jang1, Seokhyeon Jeong1, Dongsuk Jeon2, Kyojin David Choo1,
their small size and technology portability. Variability tolerance is a key design challenge when designing such PLLs in an advanced CMOS technology. Environmental variations, such as mismatch, process, supply voltage, a
Dennis Sylvester1, David Blaauw1 University of Michigan, Ann Arbor, MI
ISSCC 2017 Session 8 Digital Circuits
A 0.42ps-Jitter -241.7dB-FOM Synthesizable Injection-Locked PLL with Noise-Isolation LDO
Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima,
(ILPLL), using a noise-isolation LDO. The noise-isolation LDO realizes a time-shift operation to isolate the PLL from both supply and LDO noise, so the IL-PLL operation remains robust, even within a noisy SoC. The core l
Kenichi Okada, Akira Matsuzawa Tokyo Institute of Technology, Tokyo, J
ISSCC 2017 Session 8 Digital Circuits
A 2.5-to-5.75GHz 5mW 0.3psrms-Jitter Cascaded Ring-Based Digital Injection-Locked Clock Multiplier in 65nm CMOS
Daniel Coombs, Ahmed Elkholy, Romesh Kumar Nandwana,
traditionally used for clocking digital systems such as processors. While they are most commonly implemented using PLLs, it is becoming increasingly difficult to design them in a power efficient manner, as their jitter r
Ahmed Elmallah, Pavan Kumar Hanumolu University of Illinois, Urbana, I
ISSCC 2017 Session 8 Digital Circuits
A 0.0047mm2 Highly Synthesizable TDC- and DCOLess Fractional-N PLL with a Seamless Lock Range of fREF to 1GHz
Hwasuk Cho1, Kihwan Seong1, Kwang-Hee Choi2, Jin-Hyeok Choi2,
develop methodologies for fully automated digital design of key analog building blocks. The phase-locked loop (PLL) is a block for which an all-digital implementation has been sought recently. There have been several app
Byungsub Kim1, Hong-June Park1, Jae-Yoon Sim1 Pohang University of Sci
ISSCC 2017 Session 9 Sensors
A Resistor-Based Temperature Sensor with a 0.13pJ·K2 Resolution FOM
Sining Pan1, Yanquan Luo1,2, Saleh Heidary Shalmany1,3, Kofi A. A. Makinwa1
temperature compensation of frequency references [1-5]. High resolution and energy efficiency are then critical requirements, the former to minimize jitter and the latter to minimize power dissipation in a given conversi
Delft University of Technology, Delft, The Netherlands Ulm University,