ISSCC 2017

2017

208 篇论文 · Wireless (27) · Digital Processors (24) · Wireline I/O (24) · Memory (17) · Power Management (15)

ISSCC 2017 Session 22 Wireless
A Fully Integrated Counter-Flow Energy Reservoir for 70%-Efficient Peak-Power Delivery in Ultra-LowPower Systems
Xiao Wu, Kyojin Choo, Yao Shi, Li-Xuan Chuo, Dennis Sylvester, David Blaauw
University of Michigan, Ann Arbor, MI Recent advances in circuits have enabled significant reduction in the size of wireless systems such as implantable biomedical devices. As a consequence, the battery integrated in the
ISSCC 2017 Session 22 Wireless
An Inductively-Coupled Wireless Power-Transfer System that is Immune to Distance and Load Variations
Jiacheng Pan, Asad A. Abidi, Dejan Rozgić, Hariprasad Chandrakumar, Dejan Marković
University of California, Los Angeles, CA Biomedical implants are often powered by an external source via an inductivelycoupled wireless power link. During actual use the distance between the external and implant coils m
ISSCC 2017 Session 22 Wireless
An AC-Input Inductorless LED Driver for Visible-LightCommunication Applications with 8Mb/s Data-Rate and 6.4% Low-Frequency Flicker
Yuan Gao, Lisong Li, Philip K. T. Mok
Light-emitting diodes (LEDs) are becoming the dominant lighting source over their conventional counterparts. Besides the benefits of high efficiency and long lifetime, LEDs also show great potential for high-speed data t
ISSCC 2017 Session 23 Memory
An 8Gb 12Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications
Martin Brox1, Mani Balakrishnan1, Martin Broschwitz1,
Cristian Chetreanu1, Stefan Dietrich1, Fabien Funfrock1, Marcos Alvarez Gonzalez1, Thomas Hein1, Eugen Huber1, Daniel Lauber1, Milena Ivanov1, Maksim Kuzmenka1, Chris Mohr2, Francisco Emiliano Munoz1, Juan Ocon Garrido1,
ISSCC 2017 Session 23 Memory
A 5Gb/s/pin 8Gb LPDDR4X SDRAM with PowerIsolated LVSTL and Split-Die Architecture with 2-Die ZQ Calibration Scheme
Chang-Kyo Lee, Yoon-Joo Eom, Jin-Hee Park, Junha Lee, Hye-Ran Kim,
Kihan Kim, Young Choi, Ho-Jun Chang, Jonghyuk Kim, Jong-Min Bang, Seungjun Shin, Hanna Park, Sujin Park, Young-Ryeol Choi, Hoon Lee, Kyong-Ho Jeon, Jae-Young Lee, Hyo-Joo Ahn, Kyoung-Ho Kim, Jung-Sik Kim, Soobong Chang,
ISSCC 2017 Session 23 Memory
A 4.8Gb/s/pin 2Gb LPDDR4 SDRAM with Sub-100μA Self-Refresh Current for IoT Applications
Nohhyup Kwak, Saeng-Hwan Kim, Kyong Ha Lee, Chang-Ki Baek,
Mun Seon Jang, Yongsuk Joo, Seung-Hun Lee, Woo Young Lee, Eunryeong Lee, Donghee Han, Jaeyeol Kang, Jung Ho Lim, Jae-Beom Park, Kyung-Tae Kim, Sunki Cho, Sung Woo Han, Jee Yeon Keh, Jun Hyun Chun, Jonghoon Oh, Seok Hee L
ISSCC 2017 Session 23 Memory
An Extremely Low-Standby-Power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for Wearable Devices
Hye-Jung Kwon, Eunsung Seo, Chan-Yong Lee, Young-Hun Seo,
Gong-Heum Han, Hye-Ran Kim, Jong-Ho Lee, Min-Su Jang, Sung-Geun Do, Seung-Hyun Cho, Jae-Koo Park, Su-Yeon Doo, Jung-Bum Shin, Sang-Hoon Jung, Hyoung-Ju Kim, In-Ho Im, Beob-Rae Cho, Jae-Woong Lee, Jae-Youl Lee, Ki-Hun Yu,
ISSCC 2017 Session 23 Memory
A 4Gb LPDDR2 STT-MRAM with Compact 9F2 1T1MTJ Cell and Hierarchical Bitline Architecture
Kwangmyoung Rho1, Kenji Tsuchida2, Dongkeun Kim1, Yutaka Shirai2,
Jihyae Bae1, Tsuneo Inaba2, Hiromi Noro2, Hyunin Moon1, Sungwoong Chung1, Kazumasa Sunouchi2, Jinwon Park1, Kiseon Park1, Akihito Yamamoto2, Seoungju Chung1, Hyeongon Kim1, Hisato Oyamatsu2, Jonghoon Oh1 SK hynix Semicon
ISSCC 2017 Session 23 Memory
A 0.6V 4.266Gb/s/pin LPDDR4X Interface with AutoDQS Cleaning and Write-VWM Training for Memory Controller
Soo-Min Lee, Jihun Oh, Jinho Choi, Seokkyun Ko, Daero Kim,
Kyounghoi Koo, Jongryun Choi, Yoonjee Nam, Sangsoo Park, Hyungkweon Lee, Eunsu Kim, Sukhyun Jung, Kwanyeob Chae, Suho Kim, Sanghune Park, Sanghyun Lee, Sungho Park Samsung Electronics, Hwasung, Korea Although the LPDDR4
ISSCC 2017 Session 23 Memory
A Time-Based Receiver with 2-tap DFE for a 12Gb/s/pin Single-Ended Transceiver of Mobile DRAM Interface in 0.8V 65nm CMOS
Il-Min Yi1, Min-Kyun Chae1, Seok-Hun Hyun2, Seung-Jun Bae2,
Single-ended transceivers are mostly used for DRAM interfaces to reduce pin count. A low-supply transceiver is preferred, especially for mobile DRAM interfaces, for low-power consumption while maintaining a high-speed in
ISSCC 2017 Session 23 Memory
A 1V 7.8mW 15.6Gb/s C-PHY Transceiver Using Tri-Level Signaling for Post-LPDDR4
Woojun Choi1, Taewoong Kim1, Jongjoo Shim2, Hyungsoo Kim2,
smartphones and tablet PCs [1, 2]. Since mobile DRAM standard (LPDDR), for the next generation, targets the speed specification of 51.2GB/s, its I/O interface demands high bandwidth, low power and high efficiency. Single
ISSCC 2017 Session 23 Memory
An 8-Channel 4.5Gb 180GB/s 18ns-Row-Latency RAM for the Last Level Cache
Tah-Kang Joseph Ting1, Gyh-Bin Wang1, Ming-Hung Wang1,
Chun-Peng Wu1, Chun-Kai Wang1, Chun-Wei Lo1, Li-Chin Tien1, Der-Min Yuan1, Yung-Ching Hsieh1, Jenn-Shiang Lai2, Wen-Pin Hsu2, Chien-Chih Huang2, Chi-Kang Chen2, Yung-Fa Chou2, Ding-Ming Kwai2, Zhe Wang3, Wei Wu3, Shigeki
ISSCC 2017 Session 24 Wireless
A 770pJ/b 0.85V 0.3mm2 DCO-Based Phase-Tracking RX Featuring Direct Demodulation and Data-Aided Carrier Tracking for IoT Applications
Yao-Hong Liu1, Vijaya Kumar Purushothaman1,2, Chuang Lu1,
Johan Dijkhuis1, Robert Bogdan Staszewski2,3, Christian Bachmann1, Kathleen Philips1 Holst Centre / imec, Eindhoven, The Netherlands 2 Delft University of Technology, Delft, The Netherlands 3 University College Dublin, D
ISSCC 2017 Session 24 Wireless
A 0.1-to-3.1GHz 4-Element MIMO Receiver Array Supporting Analog/RF Arbitrary Spatial Filtering
Linxiao Zhang, Harish Krishnaswamy
Digital receiver (RX) arrays featuring ADCs at each element enable massive multiin-multi-out (MIMO) applications, but since spatial interference rejection is absent in the RF/analog domain, RF/analog/ADC dynamic range is
ISSCC 2017 Session 24 Wireless
A High-Linearity CMOS Receiver Achieving +44dBm IIP3 and +13dBm B1dB for SAW-Less LTE Radio
Yuanching Lien1,2, Eric Klumperink1, Bernard Tenbroek3, Jon Strange3, Bram Nauta1
high-linearity up-front filtering to prevent corruption of the in-band signals by strong out-of-band (OOB) signals and selfinterference from the transmitter. SAW duplexer filters are generally used for this purpose, but
ISSCC 2017 Session 24 Wireless
A 0.18V 382μW Bluetooth Low-Energy (BLE) Receiver with 1.33nW Sleep Power for Energy-Harvesting Applications in 28nm CMOS
Wei-Han Yu1, Haidong Yi1, Pui-In Mak1, Jun Yin1, Rui P. Martins1,2
Instituto Superior Tecnico, Universidade de Lisboa, Portugal 1 2 For true mobility, wearable electronics should be self-powered by the environment. On-body thermoelectric (~50μW/cm2) is a maturing energy source but deliv
ISSCC 2017 Session 24 Wireless
A 4.5nW Wake-Up Radio with -69dBm Sensitivity
Haowei Jiang, Po-Han Peter Wang, Li Gao, Pinar Sen, Young-Han Kim,
Gabriel M. Rebeiz, Drew A. Hall, Patrick P. Mercier University of California, San Diego, CA Wake-up receivers (WuRXs) are low-power radios that continuously monitor the RF environment to wake up a higher-power radio upon
ISSCC 2017 Session 24 Wireless
A Time-Interleaved Filtering-by-Aliasing Receiver Front-End with >70dB Suppression at <4×Bandwidth Frequency Offset
Sameed Hameed, Sudhakar Pamarti
Programmable receiver front-ends have been a topic of enormous interest in recent years. Both N-path filtering [1,2] and charge-domain filtering [2] achieve sharp filtering but suffer from poor matching [1] or high noise
ISSCC 2017 Session 24 Wireless
A 673μW 1.8-to-2.5GHz Dividerless Fractional-N Digital PLL with an Inherent Frequency-Capture Capability and a Phase-Dithering Spur Mitigation for IoT Applications
Yuming He1, Yao-Hong Liu1, Takashi Kuramochi2, Johan van den Heuvel1,
Belgium 1 2 The Internet-of-Things (IoT) is gaining momentum, and the ultra-low-power (ULP) RF transceiver is one of the key enablers. Generation of the local oscillator (LO) consumes a significant share of the total ene
ISSCC 2017 Session 24 Wireless
A 14nm Fractional-N Digital PLL with 0.14psrms Jitter and -78dBc Fractional Spur for Cellular RFICs
Chih-Wei Yao1, Wing Fai Loke1, Ronghua Ni1, Yongping Han1,
Haoyang Li1, Kunal Godbole1, Yongrong Zuo1, Sangsoo Ko2, Nam-Seog Kim2, Sangwook Han2, Ikkyun Jo2, Joonhee Lee2, Juyoung Han2, Daehyeon Kwon2, Chulho Kim2, Shinwoong Kim2, Sang Won Son1, Thomas Byunghak Cho2 Samsung Semi
ISSCC 2017 Session 24 Wireless
A 128-QAM 60GHz CMOS Transceiver for IEEE802.11ay with Calibration of LO Feedthrough and I/Q Imbalance
Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo,
Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Ru
ISSCC 2017 Session 25 Other
A 50.7% Peak Efficiency Subharmonic Resonant Isolated Capacitive Power Transfer System with 62mW Output Power for Low-Power Industrial Sensor Interfaces
Lei Chen1, Joseph Sankman1,2, Rajarshi Mukhopadhyay2, Mark Morgan2, D. Brian Ma1
industrial system reliability in hostile environments. They are exposed to destructive surge voltages, which are caused by ground current spikes from operation transitions of machinery and motor drives, endangering circu
ISSCC 2017 Session 25 Other
A 10MHz 3-to-40V VIN Tri-Slope Gate Driving GaN DC-DC Converter with 40.5dBμV Spurious Noise Compression and 79.3% Ringing Suppression for Automotive Applications
Xugang Ke1, Joseph Sankman1,2, Yingping Chen1, Lenian He3, D. Brian Ma1
applications, DC-DC converters are widely employed [1]. However, size and thermal limits have made it challenging to continue using standard CMOS-based converters. Gallium Nitride (GaN) FETs, on the other hand, have a mu
ISSCC 2017 Session 25 Other
A 1.3A Gate Driver for GaN with Fully Integrated Gate Charge Buffer Capacitor Delivering 11nC Enabled by High-Voltage Energy Storing
Achim Seidel, Bernhard Wicht
The MN1 control and supply circuit (Fig. 25.3.2 bottom) turns on MN1 via MN2, controlled by level shifter LS. D2 prevents discharging of the MN2 gate capacitance, when node GMN1 rises. D3 ensures 5V-over-voltage protecti
ISSCC 2017 Session 25 Other
A 500Mb/s 200pJ/b Die-to-Die Bidirectional Link with 24kV Surge Isolation and 50kV/μs CMR using Resonant Inductive Coupling in 0.18μm CMOS
Subhashish Mukherjee1, Anoop Narayan Bhat1,
Kumar Anurag Shrivastava1, Madhulatha Bonu1, Benjamin Sutton2, Venugopal Gopinathan1, Ganesan Thiagarajan1, Abhijit Patki1, Jhankar Malakar1, Nagendra Krishnapura3 Texas Instruments, Bangalore, India Texas Instruments, D
ISSCC 2017 Session 26 Digital Processors
Power Supply Noise in a 22nm z13TM Microprocessor
Pierce I-Jen Chuang1, Christos Vezyrtzis1, Divya Pathak2,
Richard Rizzolo3, Tobias Webel4, Thomas Strach4, Otto Torreiter4, Preetham Lobo5, Alper Buyuktosunoglu1, Ramon Bertran1, Michael Floyd6, Malcolm Ware6, Gerard Salem7, Sean Carey8, Phillip Restle1 IBM Research, Yorktown H
ISSCC 2017 Session 26 Digital Processors
Reconfigurable Clock Networks for Random Skew Mitigation from Subthreshold to Nominal Voltage
Longyang Lin, Saurabh Jain, Massimo Alioto
Clock network optimization is substantially affected by the operating voltage VDD, as the clock skew is dominated by different mechanisms and has a different balance between wire and repeater delay at different VDD (Fig.
ISSCC 2017 Session 26 Digital Processors
A 0.4-to-1V 1MHz-to-2GHz Switched-Capacitor Adiabatic Clock Driver Achieving 55.6% Clock Power Reduction
Loai G. Salem, Patrick P. Mercier
Clock distribution in modern SoCs consumes a significant fraction of total chip power. To reduce clock distribution power, resonant clocking schemes, where an inductive reactance is used to cancel the capacitive reactanc
ISSCC 2017 Session 26 Digital Processors
Adaptive Clocking in the POWER9TM Processor for Voltage Droop Protection
Michael S. Floyd1, Phillip J. Restle2, Michael A. Sperling3,
Pawel Owczarczyk3, Eric J. Fluhr1, Joshua Friedrich1, Paul Muench3, Timothy Diemoz3, Pierce Chuang2, Christos Vezyrtzis2 IBM, Austin, TX IBM, Yorktown Heights, NY 3 IBM, Poughkeepsie, NY 1 2 Increasing transistor counts
ISSCC 2017 Session 27 Medical & Bio
A 2.8µW 80mVpp-Linear-Input-Range 1.6GΩ-Input Impedance Bio-Signal Chopper Amplifier Tolerant to Common-Mode Interference up to 650mVpp
Hariprasad Chandrakumar, Dejan Marković
Closed-loop neuromodulation with simultaneous stimulation and sensing is desired to administer therapy in patients suffering from drug-resistant neurological ailments. However, stimulation generates large artifacts at th
ISSCC 2017 Session 27 Medical & Bio
A 25.2mW EEG-NIRS Multimodal SoC for Accurate Anesthesia Depth Monitoring
Unsoo Ha1, Jaehyuk Lee1, Jihee Lee1, Kwantae Kim1, Minseo Kim1,
monitoring of the quantitative anesthesia (ANES) depth level for safe surgery [1]. However, the current ANES depth monitoring approach, bispectral index (BIS) [3], uses only EEG from the frontal lobe, and it shows critic
ISSCC 2017 Session 27 Medical & Bio
All-Wireless 64-Channel 0.013mm2/ch Closed-Loop Neurostimulator with Rail-to-Rail DC Offset Removal
Hossein Kassiri1, M. Reza Pazhouhandeh2, Nima Soltani2,
M. Tariqus Salam3, Peter Carlen2,4, Jose Luiz Perez Velazquez2, Roman Genov2 York University, Toronto, Canada University of Toronto, Toronto, Canada 3 GSK (GlaxoSmithKline), Stevenage, United Kingdom 4 Toronto Western Ho
ISSCC 2017 Session 27 Medical & Bio
A Sub-1dB NF Dual-Channel On-Coil CMOS Receiver for Magnetic Resonance Imaging
Benjamin Sporrer1, Lianbo Wu1, Luca Bettini1, Christian Vogt1,
Jonas Reber2, Josip Marjanovic2, Thomas Burger1, David O. Brunner2, Klaas P. Prüssmann2, Gerhard Tröster1, Qiuting Huang1 ETH Zurich, Zurich, Switzerland University and ETH Zurich, Zurich, Switzerland 1 2 Magnetic Resona
ISSCC 2017 Session 27 Medical & Bio
A Pixel-Pitch-Matched Ultrasound Receiver for 3D Photoacoustic Imaging with Integrated Delta-Sigma Beamformer in 28nm UTBB FDSOI
Man-Chia Chen1, Aldo Peña Perez1, Sri-Rajasekhar Kothapalli1,
in medical ultrasound rely on 3D volumetric imaging, calling for dense 2D transducer arrays with thousands of elements. Due to this high channel count, the traditional per-element cable interface used for 1D arrays is no
ISSCC 2017 Session 27 Medical & Bio
Single-Chip 3072ch 2D Array IC with RX Analog and All-Digital TX Beamformer for 3D Ultrasound Imaging
Yusaku Katsube1, Shinya Kajiyama2, Takuma Nishimoto1,
Tatsuo Nakagawa2, Yasuyuki Okuma3, Yohei Nakamura2, Takahide Terada2, Yutaka Igarashi1, Taizo Yamawaki2, Toru Yazaki1, Yoshihiro Hayashi2, Kazuhiro Amino2, Takuya Kaneko2, Hiroki Tanaka2 Hitachi, Yokohama, Japan Hitachi,
ISSCC 2017 Session 27 Medical & Bio
A 30.5mm3 Fully Packaged Implantable Device with Duplex Ultrasonic Data and Power Links Achieving 95kb/s with <10-4 BER at 8.5cm Depth
Ting Chia Chang, Max L. Wang, Jayant Charthad, Marcus J. Weber, Amin Arbabian
invasive miniaturized solutions that operate reliably at large depths, provide duplex communication for closed-loop therapies, and enable multi-access for a network of implants to gather information or provide systemic i
ISSCC 2017 Session 27 Medical & Bio
Fully Integrated Optical Spectrometer with 500-to-830nm Range in 65nm CMOS
Lingyu Hong, Kaushik Sengupta
Next-generation IoT systems are expected to be enabled by compact, low-cost, low-power, smart sensing devices that provide a wealth of information to build new applications and capabilities. Among sensing modalities, opt
ISSCC 2017 Session 28 Data Converters
A 0.46mW 5MHz-BW 79.7dB-SNDR Noise-Shaping SAR ADC with Dynamic-Amplifier-Based FIR-IIR Filter
Chun-Cheng Liu, Mu-Chen Huang
The successive approximation register (SAR) ADC is the most energy efficient architecture with moderate conversion rate and resolution. However, its comparator noise limits its resolution without sacrificing power effici
ISSCC 2017 Session 28 Data Converters
An 11.4mW 80.4dB-SNDR 15MHz-BW CT Delta-Sigma Modulator Using 6b Double-Noise-Shaped Quantizer
Taewook Kim, Changsok Han, Nima Maghari
Quantizers are key building blocks in both continuous-time (CT) and discrete-time (DT) delta-sigma modulators (DSMs). Among various types of quantizers, noiseshaping quantizers such as VCO-based quantizers and noise-shap
ISSCC 2017 Session 28 Data Converters
A 125MHz-BW 71.9dB-SNDR VCO-Based CT ΔΣ ADC with Segmented Phase-Domain ELD Compensation in 16nm CMOS
Sheng-Jui Huang, Nathan Egan, Divya Kesharwani, Frank Opteynde, Michael Ashburn
MediaTek, Woburn, MA High-BW continuous-time ΔΣ modulators (CTDSMs), which directly inject excess loop delay compensation (ELDC) at the quantizer input, suffer from the over-range issue due to the 1+αz-1 transfer functio
ISSCC 2017 Session 28 Data Converters
A 12b 330MS/s Pipelined-SAR ADC with PVTStabilized Dynamic Amplifier Achieving <1dB SNDR Variation
Hai Huang1, Sudipta Sarkar1, Brian Elies2, Yun Chiu1
Texas Instruments, Dallas, TX 1 2 In high-speed pipeline or pipelined-SAR ADCs, conventional opamp-based residue amplifiers consume significant amounts of power due to stringent settling speed and accuracy requirements.
ISSCC 2017 Session 28 Data Converters
A 10b 1.5GS/s Pipelined-SAR ADC with Background Second-Stage Common-Mode Regulation and Offset Calibration in 14nm CMOS FinFET
Lukas Kull1, Danny Luu1,2, Christian Menolfi1, Matthias Braendli1,
Alessandro Cevrero1, Ilter Ozkaya1, Thomas Toifl1 IBM Zurich Research Laboratory, Rueschlikon, Switzerland ETH Zurich, Zurich, Switzerland 1 2 High-speed SAR ADCs became popular with modern CMOS technologies because of t
ISSCC 2017 Session 28 Data Converters
A 78.5dB-SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating up to 75MS/s with 24.9mW Power Consumption in 65nm CMOS
Hongda Xu1, Yongda Cai1, Ling Du2, Yuan Zhou3, Benwei Xu1,
Irvine, CA 4 Southern Methodist University, Dallas, TX 1 2 High-resolution, low-power radiation-tolerant ADCs are under great demand from medical, aerospace and high-energy physics applications. In the ATLAS Liquid Argon
ISSCC 2017 Session 28 Data Converters
A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm CMOS with Digital Amplifier Technique
Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim,
g. 802.11ac Wave 2 and 802.11ax draft, aim to boost user throughput to cope with growing data traffic. High-speed (fs>100MS/s) and highresolution (ENOB>9.5b) ADCs are essential for leading-edge wireless SoCs, given the b
ISSCC 2017 Session 29 Wireline I/O
A 64Gb/s 1.4pJ/b NRZ Optical-Receiver Data-Path in 14nm CMOS FinFET
Alessandro Cevrero1, Ilter Ozkaya1,3, Pier Andrea Francese1,
Christian Menolfi1, Thomas Morf1, Matthias Brandli1, Dan Kuchta2, Lukas Kull1, Jon Proesel2, Marcel Kossel1, Danny Luu1, Benjamin Lee2, Fuad Doany2, Mounir Meghelli2, Yusuf Leblebici3, Thomas Toifl1 IBM Research, Rueschl
ISSCC 2017 Session 29 Wireline I/O
A Transmitter and Receiver for 100Gb/s Coherent Networks with Integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS
Jun Cao, Delong Cui, Ali Nazemi, Tim He, Guansheng Li, Burak Catli,
Mehdi Khanpour, Kangmin Hu, Tamer Ali, Heng Zhang, Hairong Yu, Ben Rhew, Shiwei Sheng, Yonghyun Shim, Bo Zhang, Afshin Momtaz Broadcom, Irvine, CA At rates of 100Gb/s and above, CMOS DSP-based transceivers integrated wit
ISSCC 2017 Session 29 Wireline I/O
A 40Gb/s PAM-4 Transmitter Based on a RingResonator Optical DAC in 45nm SOI CMOS
Sajjad Moazeni1, Sen Lin1, Mark T. Wade2, Luca Alloatti3, Rajeev J. Ram4,
Milos A. Popovic5, Vladimir Stojanovic1 University of California, Berkeley, CA Ayar Labs, San Francisco, CA 3 ETH Zurich, Zurich, Switzerland 4 Massachusetts Institute of Technology, Cambridge, MA 5 Boston University, Bo
ISSCC 2017 Session 29 Wireline I/O
A 16Gb/s 3.6pJ/b Wireline Transceiver with Phase Domain Equalization Scheme: Integrated Pulse Width Modulation (iPWM) in 65nm CMOS
Ashwin Ramachandran, Arun Natarajan, Tejasvi Anand
Asymmetric links such as memory interfaces and display drivers require the transmitter to perform necessary equalization, while the receiver remains simple and has minimal or no equalization capability. Traditionally, FF
ISSCC 2017 Session 29 Wireline I/O
12Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling with 100% Data Payload and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces
Yeonho Lee, Yoonjae Choi, Sang-Geun Bae, Jaehun Jun,
29.5.1 is generally adopted in an intra-panel interface due to the poor signal integrity of the multi-drop topology, data and clock channel skews and EMI emission from the forwarded clock signal channels. Clock recovery
ISSCC 2017 Session 29 Wireline I/O
A 3-to-10Gb/s 5.75pJ/b Transceiver with Flexible Clocking in 65nm CMOS
Romesh Kumar Nandwana1, Saurabh Saxena2, Ahmed Elkholy1,
This 2-step truncation and cancellation method provides higher order modulation while avoiding -1 to 1 and 1 to -1 jumps, which limits the needed DCDL range to 1 cycle of CKHF, independent of output frequency/data rate.