ISSCC 2020

2020

202 篇论文 · Power Management (24) · RF & Wireless (23) · AI / ML (20) · Analog Circuits (16) · Medical & Bio (16)

ISSCC 2020 Session 32 Power Management
A 0.4-to-1.2V 0.0057mm2 55fs-Transient-FoM RingAmplifier-Based Low-Dropout Regulator with Replica-Based PSR Enhancement
Jun-Eun Park, Jeongho Hwang, Jonghyun Oh, Deog-Kyoon Jeong
Digital low-dropout regulators (DLDOs) are commonly used in low-power systemon-chips (SoCs) because of their low-voltage operation and fast transient response via the digital control of a power gate. However, the digital
Seoul National University, Seoul, Korea
ISSCC 2020 Session 32 Power Management
A Scalable and PCB-Friendly Daisy-Chain Approach to Parallelize LDO Regulators with 2.613% CurrentSharing Accuracy Using Dynamic Element Matching for Integrated Current Sensing
Bhushan Talele1, Raveesh Magod2, Keith Kunz3, Sanjeev Manandhar2, Bertan Bakkaloglu1
applications presents a challenge for chip-level thermal management and also tends to be inefficient. Straightforward parallelizing of LDOs to increase output current is a flawed approach since subtle variations between
Arizona State University, Tempe, AZ, 2Texas Instruments, Dallas, TX Te
ISSCC 2020 Session 33 Memory
A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models
Weier Wan1, Rajkumar Kubendran2, S. Burc Eryilmaz1, Wenqiang Zhang3,
Yan Liao3, Dabin Wu3, Stephen Deiss2, Bin Gao3, Priyanka Raina1, Siddharth Joshi4, Huaqiang Wu3, Gert Cauwenberghs2, H.-S. Philip Wong1 Stanford University, Stanford, CA, 2University of California, San Diego, CA, Tsinghu
ISSCC 2020 Session 33 AI / ML
A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing cell is signed quasi-2-bit (3-level) or signed quasi-3-bit (7-level) accordingly.
According to the off-chip test on the same ReRAM stacks, the device conductance, could be tuned continuously. However, t
on-chip ReRAM conductance could be quantified with 256 states at most. Qi Liu1, Bin Gao1, Peng Yao1, Dong Wu1, Junren Chen1, Yachuan Pang1, Wenqiang Zhang1, Yan Liao1, Cheng-Xin Xue2, Wei-Hao Chen2, Jianshi Tang1, Yu Wan
ISSCC 2020 Session 33 Memory
Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications
Masanori Hashimoto1, Xu Bai2, Naoki Banno2, Munehiro Tada2,
Toshitsugu Sakamoto2, Jaehoon Yu1, Ryutaro Doi1, Yusuke Araki3, Hidetoshi Onodera3, Takashi Imagawa4, Hiroyuki Ochi4, Kazutoshi Wakabayashi5, Yukio Mitsuyama6, Tadahiko Sugibayashi2 Osaka University, Suita, Japan, 2NEC,
ISSCC 2020 Session 34 Medical & Bio
A 64×64 Implantable Real-Time Single-ChargedParticle Radiation Detector for Cancer Therapy
Kyoungtae Lee1, Jessica Scholey2, Eric B. Norman1, Inder K. Daftari2,
Kavita K. Mishra2, Bruce A. Faddegon2, Michel M. Maharbiz1, Mekhail Anwar2 University of California, Berkeley, CA 2 University of California, San Francisco, CA 1 60% of all cancer treatment requires radiation therapy and
ISSCC 2020 Session 34 AI / ML
1225-Channel Localized Temperature-Regulated Neuromorphic Retinal-Prosthesis SoC with 56.3nW/Channel Image Processor
Jeong Hoan Park1, Joanne Si Ying Tan 1, Han Wu1, Jerald Yoo1,2
N.1 Institute for Health, Singapore, Singapore 1 2 Retinal prosthesis (RP) electrically stimulates the retinal cells of the blind to restore visual loss, and it is essential to increase the number of channels for higher
National University of Singapore, Singapore, Singapore
ISSCC 2020 Session 34 Medical & Bio
An 8.2mm3 Implantable Neurostimulator with Magnetoelectric Power and Data Transfer
Zhanghao Yu*, Joshua C. Chen*, Benjamin W. Avants, Yan He,
Amanda Singer, Jacob T. Robinson, Kaiyuan Yang Rice University, Houston, TX *Equally-Credited Authors (ECAs) Modulating the electrical activity in the nervous system has shown great potential for neuroscience research an
ISSCC 2020 Session 34 Medical & Bio
A 4.5mm3 Deep-Tissue Ultrasonic Implantable Luminescence Oxygen Sensor
Soner Sonmezoglu, Michel M. Maharbiz
Continuous monitoring of regional tissue oxygenation (RTO) can provide therapeutic guidance for critical care patients. Current technologies for RTO assessment require tethered, wired connections or batteries, creating p
University of California, Berkeley, CA
ISSCC 2020 Session 34 Medical & Bio
Human-Body-Coupled Power-Delivery and AmbientEnergy-Harvesting ICs for a Full-Body-Area Power Sustainability is performed for bulk connection with the VRECT and GND at input amplitude higher than 0.6V, so that the body diode forward biasing is aligned with the conduction path. As a result, at 5V TX swing, 3.5μW power is recovered from ankle to forehead (160cm), successfully covering the whole body.
Jiamin Li*1, Yilong Dong*1, Jeong Hoan Park1, Longyang Lin1, Tao Tang1,
Miaolin Zhang1, Han Wu1, Lian Zhang1, Joanne Si Ying Tan1, Jerald Yoo1,2 Figure 34.5.4 shows the proposed Dual-Mode Buck-Boost Converter (DM-BBC). Due to the unpredictability of the environmental parasitic and the variat
ISSCC 2020 Session 34 Medical & Bio
EEG Dust: A BCC-Based Wireless Concurrent Recording/Transmitting Concentric Electrode
Tao Tang1, Long Yan2, Jeong Hoan Park1, Han Wu1, Lian Zhang1,
Institute for Health, Singapore, Singapore 1 2 EEG recording technology creates the opportunity to sense and discover potential fluctuation in the human brain [1]. Quantitative analysis based on various EEG sensor nodes
Ho Yin Benjamin Lee1, Jerald Yoo1,3 National University of Singapore,
ISSCC 2020 Session 4 Wireless
A 39GHz-Band CMOS 16-Channel Phased-Array Transceiver IC with a Companion Dual-Stream IF Transceiver IC for 5G NR Base-Station Applications
H.-C. Park, D. Kang, S. M. Lee, B. Park, K. Kim, J. Lee, Y. Aoki, Y. Yoon,
S. Lee, D. Lee, D. Kwon, S. Kim, J. Kim, W. Lee, C. Kim, S. Park, J. Park, B. Suh, J. Jang, M. Kim, D. Minn, I. Park, S. Kim, K. Min, J. Park, S. Jeon, A.-S. Ryu, Y. Cho, S. T. Choi, K. H. An, Y. Kim, J. H. Lee, J. Son,
ISSCC 2020 Session 4 Wireless
An E-Band High-Linearity Antenna-LNA Front-End with 4.8dB NF and 2.2dBm IIP3 Exploiting Multi-Feed On-Antenna Noise-Canceling and Gm-Boosting
Sensen Li1, Taiyun Chi1,2, Doohwan Jung1, Tzu-Yuan Huang1,
paradigm to advance front-end innovations and performance beyond electronics-only designs. Instead of being viewed as single-port 50Ω radiation loads, antennas are perceived as multi-feed passive networks interfacing wit
Min-Yu Huang1, Hua Wang1 Georgia Institute of Technology, Atlanta, GA
ISSCC 2020 Session 4 Wireless
A 28GHz 4-Element MIMO Beam-Space Array in 65nm CMOS with Simultaneous Spatial Filtering and Single-Wire Frequency-Domain Multiplexing
Robin Garg1, Gaurav Sharma*1, Ali Binaie*2, Sanket Jain*1,
(ECAs) 1 2 High-data-rate wireless links at mm-wave have motivated the development of scalable, dense arrays with hundreds of elements [1,2]. The evolution from “multiple-input-single-output” phased arrays towards multib
Sohail Ahasan*2, Armagan Dascurcu2, Harish Krishnaswamy2, Arun Nataraj
ISSCC 2020 Session 4 Wireless
A 64Gb/s 1.4pJ/b/element 60GHz 2×2-Element Phased-Array Receiver with 8b/symbol Polarization MIMO and Spatial Interference Tolerance
Anandaroop Chakrabarti, Chintan Thakkar, Shuhei Yamada,
multi-user connectivity [1]. Despite this opportunity, throughput of 60GHz phased arrays has been limited to 10.4Gb/s [2-5], and therefore may not offer a substantial performance benefit over the rapidly improving sub-7G
Debabani Choudhury, James Jaussi, Bryan Casper Intel, Hillsboro, OR Th
ISSCC 2020 Session 4 Wireless
Space-Time Modulated 71-to-76GHz mm-Wave Transmitter Array for Physically Secure Directional Wireless Links
Xuyang Lu*1, Suresh Venkatesh*1, Bingjun Tang2, Kaushik Sengupta1
Xi'an Jiaotong University, Xi'an, China *Equally-Credited Authors (ECAs) 1 2 Security in wireless networks has traditionally been addressed above the physical layer. With the expected proliferation of applications in 5G,
Princeton University, Princeton, NJ
ISSCC 2020 Session 4 Wireless
A Single-Antenna W-Band FMCW Radar Front-End Utilizing Adaptive Leakage Cancellation
Milad Kalantari1,2, Hossein Shirinabadi3, Ali Fotowat-Ahmadi2, C. Patrick Yue1
radars are essential for automotive sensing, medical imaging, and safety- monitoring applications. Among different architectures, frequencymodulated continuous-wave (FMCW) radars are particularly suited for miniature int
Hong Kong University of Science and Technology, Hong Kong, China Shari
ISSCC 2020 Session 4 Wireless
A Terahertz FMCW Comb Radar in 65nm CMOS with 100GHz Bandwidth
Xiang Yi1, Cheng Wang1, Muting Lu1, Jinchen Wang1, Jesus Grajal1,2, Ruonan Han1
systems have driven the operation frequency to terahertz (THz) due to the shorter wavelength and larger bandwidth [1-5]. However, conventional single-transceiver FMCW radar chips only provide limited signal bandwidth (<7
Massachusetts Institute of Technology, Cambridge, MA 2 Universidad Pol
ISSCC 2020 Session 5 Image Sensors
A 240×192Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm2 Voltage/Time Dual-Data-Converter-Based AFE
Satoshi Kondo1, Hiroshi Kubota2, Hisaaki Katagiri2, Yutaka Ota2,
Masatoshi Hirono3, Tuan Thanh Ta1, Hidenori Okuni1, Shinichi Ohtsuka2, Yoshinari Ojima2, Tomohiko Sugimoto2, Hirotomo Ishii2, Kentaro Yoshioka1, Katsuyuki Kimura2, Akihide Sai1, Nobu Matsumoto2 Toshiba, Kawasaki, Japan T
ISSCC 2020 Session 5 Image Sensors
A 1280×720 Back-Illuminated Stacked Temporal Contrast Event-Based Vision Sensor with 4.86µm
Pixels, 1.066GEPS Readout, Programmable Event-Rate, Controller and Compressive Data-Formatting Pipeline
Thomas Finateu1, Atsumi Niwa2, Daniel Matolin1, Koya Tsuchimoto2, Andrea Mascheroni1, Etienne Reynaud 1, Pooria Mostafalu3, Frederick Brady3, Ludovic Chotard1, Florian LeGoff1, Hirotsugu Takahashi2, Hayato Wakabayashi2,
ISSCC 2020 Session 5 Image Sensors
A 1200×900 6µm 450fps Geiger-Mode Vertical Avalanche Photodiodes CMOS Image Sensor for a 250m Time-of-Flight Ranging System Using Direct-IndirectMixed Frame Synthesis with Configurable-DepthResolution Down to 10cm
Toru Okino, Shota Yamada, Yusuke Sakata, Shigetaka Kasuga,
Masato Takemoto, Yugo Nose, Hiroshi Koshida, Masaki Tamaru, Yuki Sugiura, Shigeru Saito, Shinzo Koyama, Mitsuyoshi Mori, Yutaka Hirose, Masayuki Sawada, Akihiro Odagawa, Tsuyoshi Tanaka Panasonic, Nagaokakyo, Japan Long-
ISSCC 2020 Session 5 Image Sensors
An Up-to-1400nm 500MHz Demodulated Time-ofFlight Image Sensor on a Ge-on-Si Platform
C.-L. Chen*, S.-W. Chu*, B.-J. Chen*, Y.-F. Lyu*, K.-C. Hsu*,
C.-F. Liang*, S.-S. Su, M.-J. Yang, C.-Y. Chen, S.-L. Cheng, H.-D. Liu, C.-T. Lin, K. P. Petrov, H.-W. Chen, K.-C. Chu, P.-C. Wu, P.-T. Huang, N. Na, S.-L. Chen Artilux, Hsinchu, Taiwan, *Equally-Credited Authors (ECAs)
ISSCC 2020 Session 5 Image Sensors
A Dynamic Pseudo 4-Tap CMOS Time-of-Flight Image Sensor with Motion Artifact Suppression and Background Light Cancelling Over 120klux
Donguk Kim1, Seunghyun Lee2, Dahwan Park2, Canxing Piao1,
Jihoon Park1, Yeonsoo Ahn1, Kihwan Cho1, Jungsoon Shin3, Seung Min Song3, Seong-Jin Kim2, Jung-Hoon Chun1, Jaehyuk Choi1 Sungkyunkwan University, Suwon, Korea Ulsan National Institute of Science and Technology, Ulsan, Ko
ISSCC 2020 Session 5 Image Sensors
A 2.1e- Temporal Noise and -105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology
Jae-kyu Lee, Seung Sik Kim, In-Gyu Baek, Heesung Shim, Taehoon Kim,
Taehyoung Kim, Jungchan Kyoung, Dongmo Im, Jinyong Choi, KeunYeong Cho, Daehoon Kim, Haemin Lim, Min-Woong Seo, JuYoung Kim, Doowon Kwon, Jiyoun Song, Jiyoon Kim, Minho Jang, Joosung Moon, HyunChul Kim, Chong Kwang Chang
ISSCC 2020 Session 5 Image Sensors
A 1/2.65in 44Mpixel CMOS Image Sensor with 0.7µm Pixels Fabricated in Advanced Full-Depth Deep-Trench Isolation Technology
HyunChul Kim, Jongeun Park, Insung Joe, Doowon Kwon,
Joo Hyoung Kim, Dongsuk Cho, Taehun Lee, Changkyu Lee, Haeyong Park, Soojin Hong, Chongkwang Chang, Jingyun Kim, Hanjin Lim, Youngsun Oh, Yitae Kim, Seungjoo Nah, Sangill Jung, Jaekyu Lee, JungChak Ahn, Hyeongsun Hong, K
ISSCC 2020 Session 5 Image Sensors
A 132dB Single-Exposure-Dynamic-Range CMOS Image Sensor with High Temperature Tolerance
Yorito Sakano1, Takahiro Toyoshima1, Ryosuke Nakamura1,
Tomohiko Asatsuma1, Yuki Hattori1, Takayuki Yamanaka2, Ryoichi Yoshikawa2, Naoki Kawazu1, Tomohiro Matsuura1, Takahiro Iinuma1, Takahiro Toya1, Tomohiko Watanabe2, Atsushi Suzuki1, Yuichi Motohashi1, Junichiro Azami1, Ya
ISSCC 2020 Session 5 Image Sensors
A 0.50e-rms Noise 1.45µm-Pitch CMOS Image Sensor with Reference-Shared In-Pixel Differential Amplifier at 8.3Mpixel 35fps
Mamoru Sato, Yuhi Yorikado, Yusuke Matsumura, Hideki Naganuma,
dark and bright conditions. In recent years, these features have been required for small pixel CMOS image sensors (CISs) to realize high S/N and resolutions while maintaining a high frame rate. An effective way to improv
Eriko Kato, Takuya Toyofuku, Akihiko Kato, Yusuke Oike Sony Semiconduc
ISSCC 2020 Session 5 Image Sensors
A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel
Tzu-Hsiang Hsu*, Yen-Kai Chen*, Jun-Shen Wu, Wen-Chien Ting,
Cheng-Te Wang, Chen-Fu Yeh, Syuan-Hao Sie, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh National Tsing Hua University, Hsinchu, Taiwan, *Equally-Credited Authors (ECAs) Ener
ISSCC 2020 Session 6 Wireline I/O
A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET
Jay Im1, Kevin Zheng1, Adam Chou1, Lei Zhou1, Jae Wook Kim1,
Stanley Chen1, Yipeng Wang2, Hao-Wei Hung2, KeeHian Tan2, Winson Lin1, Arianne Roldan1, Declan Carey3, Ilias Chlis3, Ronan Casey3, Ade Bekele1, Ying Cao1, David Mahashin1, Hong Ahn1, Hongtao Zhang1, Yohan Frans1, Ken Cha
ISSCC 2020 Session 6 Wireline I/O
A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology
Tamer Ali*1, Ehung Chen*1, Henry Park*1, Ramy Yousry*1,
Yu-Ming Ying1, Mohammed Abdullatif1, Miguel Gandara1, Chun-Cheng Liu2, Po-Shuan Weng2, Huan-Sheng Chen2, Mohammad Elbadry1, Qaiser Nehal1, Kun-Hung Tsai2, Kevin Tan2, Yi-Chieh Huang2, Chung-Hsien Tsai2, Yuyun Chang2, Yua
ISSCC 2020 Session 6 Wireline I/O
A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET
Eric Groen1, Charlie Boecker1, Masum Hossain2, Roxanne Vu1,
Socrates Vamvakos1, Haidang Lin1, Simon Li1, Marcus van Ierssel3, Prashant Choudhary1, Nanyan Wang1, Masumi Shibata3, Mohammad Hossein Taghavi3, Nhat Nguyen1,4, Shaishav Desai1 Rambus, Sunnyvale, CA, 2University of Alber
ISSCC 2020 Session 6 Wireline I/O
A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier
Byoung-Joo Yoo, Dong-Hyuk Lim, Hyonguk Pang, June-Hee Lee,
Seung-Yeob Baek, Naxin Kim, Dong-Ho Choi, Young-Ho Choi, Hyeyeon Yang, Taehun Yoon, Sang-Hyeok Chu, Kangjik Kim, Woochul Jung, Bong-Kyu Kim, Jaechol Lee, Gunil Kang, Sang-Hune Park, Michael Choi, Jongshin Shin Samsung El
ISSCC 2020 Session 6 Wireline I/O
A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS
Kwanseo Park, Minkyo Shim, Han-Gon Ko, Deog-Kyoon Jeong
Continuous-rate referenceless clock and data recovery (CDR) circuits are capable of operating over a wide range of data rates in multiple standards. To achieve wide-range operation without an external reference clock, se
Seoul National University, Seoul, Korea
ISSCC 2020 Session 6 Wireline I/O
Reference-Noise Compensation Scheme for SingleEnded Package-to-Package Links
Xi Chen1, Nikola Nedovic1, Stephen G. Tell2, Sudhir S. Kudva1,
Brian Zimmer1, Thomas H. Greer2, John W. Poulton2, Sanquan Song1, Walker J. Turner2, John M. Wilson2, C. Thomas Gray2 NVIDIA, Santa Clara, CA NVIDIA, Durham, NC 1 2 A recent trend in high-performance systems is distribut
ISSCC 2020 Session 6 Wireline I/O
An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels
Han-Gon Ko, Soyeong Shin, Jonghyun Oh, Kwanseo Park, Deog-Kyoon Jeong
a silicon interposer technology to increase the number of I/O pins. Interfaces with the silicon interposer provide a higher throughput (Gb/s/µm) than other packaging technologies due to the high channel density. To incre
Seoul National University, Seoul, Korea To meet the demand for high me
ISSCC 2020 Session 6 Wireline I/O
A 100Gb/s NRZ Transmitter with 8-Tap FFE Using a 7b DAC in 40nm CMOS
Pen-Jui Peng1, Sheng-Tsung Lai1, Wei-Hung Wang1, Chiang-Wei Lin1,
satisfy the continuously growing demands for wireline communications [1-5]. Although PAM-4 signaling performs two-fold bandwidth efficiency compared with the NRZ counterpart, the NRZ signal still has the advantage in low
Wei-Chien Huang1, Ted Shih2 Yuan Ze University, Taoyuan, Taiwan 2 Tele
ISSCC 2020 Session 7 AI / ML
A 3.4-to-13.3TOPS/W 3.6TOPS Dual-Core Deep-Learning Accelerator for Versatile AI Applications in 7nm 5G Smartphone SoC
Chien-Hung Lin, Chih-Chung Cheng, Yi-Min Tsai, Sheng-Je Hung,
Yu-Ting Kuo, Perry H Wang, Pei-Kuei Tsung, Jeng-Yun Hsu, Wei-Chih Lai, Chia-Hung Liu, Shao-Yu Wang, Chin-Hua Kuo, Chih-Yu Chang, Ming-Hsien Lee, Tsung-Yao Lin, Chih-Cheng Chen MediaTek, Hsinchu, Taiwan Recent advancement
ISSCC 2020 Session 7 AI / ML
A 12nm Programmable Convolution-Efficient Neural-Processing-Unit Chip Achieving 825TOPS
Yang Jiao1, Liang Han1, Rong Jin2, Yi-Jung Su1, Chiente Ho1, Li Yin3,
Yun Li1, Long Chen1, Zhen Chen1, Lu Liu3, Zhuyu He3, Yu Yan3, Jun He3, Jun Mao3, Xiaotao Zai3, Xuejun Wu3, Yongquan Zhou3, Mingqiu Gu1, Guocai Zhu1, Rong Zhong1, Wenyuan Lee1, Ping Chen1, Yiping Chen1, Weiliang Li3, Deyu
ISSCC 2020 Session 7 AI / ML
STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-SpinUpdates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions
Kasho Yamamoto1,2, Kota Ando1, Normann Mertig3, Takashi Takemoto3,
Masanao Yamaoka3, Hiroshi Teramoto2, Akira Sakai2, Shinya Takamaeda-Yamazaki4, Masato Motomura1 Tokyo Institute of Technology, Yokohama, Japan Hokkaido University, Sapporo, Japan, 3Hitachi, Sapporo, Japan 4 University of
ISSCC 2020 Session 7 AI / ML
GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation
Sanghoon Kang, Donghyeon Han, Juhyoung Lee, Dongseok Im,
image style transfer to synthetic voice generation [1]. GAN applications on mobile devices, such as face-to-Emoji conversion and super-resolution imaging, enable more engaging user interaction. As shown in Fig. 7.4.1, a
Sangyeob Kim, Soyeon Kim, Hoi-Jun Yoo KAIST, Daejeon, Korea Generative
ISSCC 2020 Session 8 Industry Highlights
Lakefield and Mobility Compute: A 3D Stacked 10nm and
22FFL Hybrid Processor System in 12×12mm2, 1mm, Package-on-Package
Wilfred Gomes1, Sanjeev Khushu2, Doug B. Ingerly1, Patrick N. Stover3, Nasirul I. Chowdhury1, Frank O'Mahony1, Ajay Balankutty1, Noam Dolev3, Martin G. Dixon1, Lei Jiang1, Surya Prekke4, Biswajit Patra4, Pavel V. Rott1,
ISSCC 2020 Session 8 Industry Highlights
A Versatile 7nm Adaptive Compute Acceleration Platform Processor
Prasun K. Raha, Tomai Knopp, Sagheer Ahmad, Ahmad Ansari,
Fu-Hing Ho, Thomas To, Vamsi Nalluri, Mrinal Sarmah, Rajeev Patwari Xilinx, San Jose, CA As benefits from Moore’s Law diminish [1], general-purpose compute platforms like CPUs and GPUs continue to become increasingly pow
ISSCC 2020 Session 8 Industry Highlights
A 3GHz ARM Neoverse N1 CPU in 7nm FinFET for Infrastructure Applications
Robert Christy1, Stuart Riches2, Sujil Kottekkat3, Prasanth Gopinath4,
Ketan Sawant3, Anitha Kona1, Rob Harrison3 ARM, Austin, TX ARM, Cambridge, United Kingdom 3 ARM, Sheffield, United Kingdom 4 ARM, Bangalore, India 1 2 The Neoverse family of Arm processors target a combination of high pe
ISSCC 2020 Session 8 Industry Highlights
Radeon RX 5700 Series: The AMD 7nm Energy-Efficient High-Performance GPUs
Sal Dasgupta1, Teja Singh2, Ashish Jain2, Samuel Naffziger3,
technology, the design of the Radeon RX 5700 series GPUs incorporate a 256b memory interface of GDDR6 memory operating at 14Gb/s for a total of 448GB/s bandwidth, a x16 PCIe® Gen4 link interface, and six 1.4 Display Port
Deepesh John2, Chetan Bisht4, Pradeep Jayaraman1 AMD, Santa Clara, CA
ISSCC 2020 Session 9 Data Converters
A Current-Sensing Front-End Realized by A ContinuousTime Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s
Su-Hao Wu*, Yun-Shiang Shu*, Albert Yen-Chih Chiou,
are widely used in various applications, such as photoplethysmography (PPG) recording by biomedical sensors and molecular-concentration detection by electrochemical sensors. They usually require a low noise level down to
Wei-Hsiang Huang, Zhi-Xin Chen, Hung-Yi Hsieh MediaTek, Hsinchu, Taiwa
ISSCC 2020 Session 9 Data Converters
A 134µW 24kHz-BW 103.5dB-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-Level FIR DAC
MoonHyung Jang, Changuk Lee, Youngcheol Chae
Audio applications require a high-resolution ADC with a dynamic range (DR) of more than 100dB. A continuous-time delta-sigma modulator (CTDSM) is widely used to realize such ADCs and requires high energy efficiency for b
Yonsei University, Seoul, Korea
ISSCC 2020 Session 9 Data Converters
A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping
Jiaxin Liu1, Xing Wang1, Zijie Gao1, Mingtao Zhan1, Xiyuan Tang2, Nan Sun2
have drawn increasing attention due to their simplicity, low power, zero static current, and PVT robustness. However, prior works show limited resolution (ENOB(13b) due to two main challenges. The 1st one is thermal nois
Tsinghua University, Beijing, China University of Texas, Austin, TX 1
ISSCC 2020 Session 9 Data Converters
A 4th-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100kHz Bandwidth
Lu Jie, Boyi Zheng, Hsiang-Wen Chen, Runyu Wang, Michael P. Flynn
High-resolution, sub-MHz-bandwidth data converters are essential for audio and sensor applications and are conventionally implemented as sigma-delta (SD) converters. The dependence of SD ADCs on op-amps inherently result
University of Michigan, Ann Arbor, MI
ISSCC 2020 Session 9 Data Converters
A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier
Xiyuan Tang1, Xiangxing Yang1, Wenda Zhao1, Chen-Kai Hsu1, Jiaxin Liu2,
Linxiao Shen1, Abhishek Mukherjee1, Wei Shi1, David Z. Pan1, Nan Sun1 University of Texas, Austin, TX, 2Tsinghua University, Beijing, China 1 Noise shaping (NS) SAR ADCs combine the merits of SAR and ∆Σ ADCs, and can sim
ISSCC 2020 Session 9 Data Converters
A 2.56mW 40MHz-Bandwidth 75dB-SNDR PartialInterleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration
Yan Song1, Yan Zhu1, Chi Hang Chan1, Rui Paulo Martins1,2
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 The noise-shaping SAR (NS-SAR) hybrid architecture has shown its potential in achieving tens of MHz bandwidth (BW) together with high resolution [1-2]
University of Macau, Macau, China