ISSCC 2020
Session 25
Digital Circuits
A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique are generated from the reference frequency, to perform a frequency-shaping SSPD, the associated switch size needs to be minimized to avoid additional spurs at the output.
These PLLs exhibit features like small area, large tuning range, and multiple output phases. However, their jitter performance is worse than that in LC-oscillator-based PLLs. Although a wider PLL bandwidth can reduce the
ISSCC 2020
Session 25
Digital Circuits
Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS
Gregory Chen1, Monodeep Kar1, Raghavan Kumar1, Huseyin Sumbul1, Phil Knag1, Himanshu Kaul1, Sanu Mathew1, Mahesh Kumashikar2, Ram Krishnamurthy1, Vivek De1 Intel, Hillsboro, OR Intel, Bangalore, India 1 2 Flip-flops (FFs
ISSCC 2020
Session 25
Digital Circuits
A Near-Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain UltraLow-Power System-on-a-Chip
demand a new system-on-a-chip (SoC) that is ultra-low power (mW or even sub-mW level) but highly robust. Such an SoC typically integrates heterogeneous building blocks for supporting a range of features, each ideally ope
ISSCC 2020
Session 25
Digital Circuits
Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for HighPerformance Processors with Wide Voltage-Frequency Operating Range
Raghavan Kumar, H. Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De Intel, Hillsboro, OR The clock frequency of high-performance processo
ISSCC 2020
Session 26
AI / ML
A Neuromorphic Multiplier-Less Bit-Serial WeightMemory-Optimized 1024-Tree Brain-State Classifier and Neuromodulation SoC with an 8-Channel Noise-Shaping SAR ADC Array
Camilo Tejeiro1, Maged ElAnsary1, Chenxi Tang1, Homeira Moradi2, Prajay Shah1, Taufik A. Valiante3, Roman Genov1 University of Toronto, Toronto, Canada Krembil Neuroscience Center, Toronto, ON, Canada 3 Toronto Western H
ISSCC 2020
Session 26
Medical & Bio
A Closed-Loop Neuromodulation Chipset with 2-Level Classification Achieving 1.5Vpp CM Interference
Aerosemi Technology, Xi'an, China 1 2 In closed-loop neuromodulators for epilepsy patients, nonidealities such as common-mode interference (CMI), stimulation artifacts (SA), electrode DC offset (DCO) and 1/f noise bring
ISSCC 2020
Session 26
Medical & Bio
A Cell-Capacitance-Insensitive CMOS Sample-and-Hold Chronoamperometric Sensor for Real-Time Measurement of Small Molecule Drugs in Whole Blood exponential model). Most of the signal-of-interest lies within the first 10ms after the potential stepping, indicating that the ADC can be further powered off during the other 90ms. The sensor front-end is configured to perform SWV calibration every few tens of minutes to track drift in the redox potential.
with a tail current of 320µA are employed in the DAC reference buffer, the current conveyor, and the potentiostat. The Miller-compensated RC network in the potentiostat is removed to avoid instability. To minimize leakag
ISSCC 2020
Session 26
Medical & Bio
A 20µW Heartbeat Detection System-on-Chip Powered by Human Body Heat for Self-Sustaining Wearable Healthcare
*Equally-Credited Authors (ECAs) Wearable devices are expanding beyond consumer and entertainment applications, including continuous monitoring of vital signs for medical diagnostics, due to extended ambulatory measureme
ISSCC 2020
Session 26
Medical & Bio
A 6.5µW 10kHz-BW 80.4dB-SNDR Continuous-Time ΔΣ Modulator with Gm-Input and 300mVpp Linear Input Range for Closed-Loop Neural Recording
Kwandong University International St. Mary’s Hospital, Incheon, Korea 1 2 Closed-loop neural recording requires a front-end with a wide DR to record small neural signals without distortion in the presence of a DC electro
ISSCC 2020
Session 26
Medical & Bio
A 280µW 108dB DR Readout IC with Wireless Capacitive Powering Using a Dual-Output Regulating Rectifier for Implantable PPG Recording
The development of advanced neuroprostheses for restoration of function after spinal cord injury (SCI) is one of the most rapidly growing directions for neuroengineering research. Among the most exciting solutions is a n
ISSCC 2020
Session 26
Medical & Bio
A Trimodal Wireless Implantable Neural Interface System-on-Chip
5Bionic Sciences, Atlanta, GA 1 3 Implantable biomedical devices (IMDs) capable of injecting a designated current into target neural tissue to modulate neural activity have been proven therapeutically effective. The next
ISSCC 2020
Session 26
Medical & Bio
A 0.19×0.17mm2 Wireless Neural Recording IC for Motor Prediction with Near-Infrared-Based Power and Data Telemetry
Paras R. Patel1, Parag G. Patil1, Sechang Oh1, Inhee Lee1, Hun-Seok Kim1, Dennis Sylvester1, David Blaauw1, Cynthia A. Chestek1, Jamie Phillips1, Taekwang Jang2 University of Michigan, Ann Arbor, MI ETH Zürich, Zürich, S
ISSCC 2020
Session 27
Hardware Security
A 65nm Energy-Harvesting ULP SoC with 256kB CortexM0 Enabling an 89.1µW Continuous Machine Health Monitoring Wireless Self-Powered System
Kyle Craig2, Greg Glennon2, Kuo-Ken Huang3, Christopher J. Lukas2, William Moore3, Richard K. Sawyer2, Yousef Shakhsheer2,4, Farah B. Yahya2, Alice Wang3, Nathan E. Roberts2, David D. Wentzloff1, Benton H. Calhoun2 Evera
ISSCC 2020
Session 27
Hardware Security
M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power
Jonas Svedas1, Matthew J Walker1, Supreet Jeloka2, Philex Ming-Yan Fan1, Fernando García-Redondo1, Thanusree Achuthan1, James Myers1 ARM, Cambridge, United Kingdom, 2ARM, Austin, TX 1 Recent research has shown subthresho
ISSCC 2020
Session 27
Hardware Security
EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation
Shovan Maity1, Baibhab Chatterjee1, Donghyun Seo1, Muya Chang2, Avinash Varna3, Harish Krishnamurthy4, Sanu Mathew4, Santosh Ghosh4, Arijit Raychowdhury2, Shreyas Sen1 Purdue University, West Lafayette, IN Georgia Instit
ISSCC 2020
Session 27
Hardware Security
Physically Unclonable Function in 28nm FDSOI Technology Achieving High Reliability for AEC-Q100 Grade 1 and ISO26262 ASIL-B
Physically Unclonable Functions (PUFs) are considered a secure method for security key generation because they generate responses that exist only during operation. A challenge regarding the use of PUFs is to achieve high
ISSCC 2020
Session 28
Medical & Bio
A Capacitive Touch Chipset with 33.9dB ChargeOverflow Reduction Using Amplitude-Modulated Multi-Frequency Excitation and Wireless Power and Data Transfer to an Active Stylus
systems (CTSs), several driving methods have been reported [1-5]. However, when excitation circuits simultaneously send excitation signals (VEXTs) to multiple TX electrodes in order to increase frame rate, the readout ci
ISSCC 2020
Session 28
Medical & Bio
A 51dB-SNR 120Hz-Scan-Rate 32×18 Segmented-VCOM LCD In-Cell Touch-Display-Driver IC with 96-Channel Compact Shunt-Sensing Self-Capacitance Analog Front-End
display implementation have been undertaken in recent years, with several being successfully delivered to the industry and market. As a result, in-cell touch-display solutions that offer low-profile formfactor, low modul
ISSCC 2020
Session 28
Medical & Bio
A 5.2Mpixel 88.4dB-DR 12in CMOS X-Ray Detector with 16b Column-Parallel Continuous-Time ΔΣ ADCs
a full image depth even for a specific region of interest, and require high resolution, low noise, and wide DR in a wafer-scale detector [1-4]. To achieve a wide DR, a large integration capacitor is required within the p
ISSCC 2020
Session 28
Medical & Bio
A CMOS Multimodality In-Pixel Electrochemical and Impedance Cellular Sensing Array for Massively Paralleled Synthetic Exoelectrogen Characterization current/charge-transfer with CV and CA tests. The generated current from cell samples is integrated on the feedback capacitor (50 to 150fF) of the in-pixel capacitive-TIA (CTIA), and 2-point measurements extract the output integration slope to remove flicker noise and fixed pattern noise.
Sara Tejedor Sanz3, Sandra Grijalva4, Adam Wang1, Sensen Li1, Hee Cheol Cho4, Caroline Ajo-Franklin5, Hua Wang1 The complex cellular impedance sensing circuit is illustrated in Fig. 28.4.3. The two WEs in each pixel oper
ISSCC 2020
Session 29
RF & Wireless
A 0.42THz 9.2dBm 64-Pixel Source-Array SoC with Spatial Modulation Diversity for Computational Terahertz Imaging
Computational THz Imaging (CTI) is the process of indirectly forming images using algorithms that rely on a significant amount of computing. Unlike focalplane arrays (FPAs), a single-pixel camera (SPC) uses spatially pat
ISSCC 2020
Session 29
RF & Wireless
A 0.59THz Beam-Steerable Coherent Radiator Array with 1mW Radiated Power and 24.1dBm EIRP in 40nm CMOS
In THz imaging systems, signal sources are needed to provide illumination of objects. In several reported imaging systems working at 0.3THz, 0.62THz, and 0.81THz, an output power around 1mW is required to achieve an acce
ISSCC 2020
Session 29
RF & Wireless
Non-Magnetic 0.18µm SOI Circulator with Multi-Watt Power Handling Based on Switched-Capacitor Clock Boosting
There has been significant recent progress in the implementation of integrated non-reciprocal components based on linear periodically-time-varying (LPTV) circuits [1-5]. Nevertheless, integrated circulators still require
ISSCC 2020
Session 29
RF & Wireless
High-Performance Isolators and Notch Filters Based on N-Path Negative Transresistance
circuits are used for a variety of functions, including the realization of oscillators and loss compensation. Active negative-resistance circuits, such as cross-coupled gm cells, can provide power gain but, when used for
ISSCC 2020
Session 29
RF & Wireless
Sub-THz CMOS Molecular Clock with 43ppt Long-Term Stability Using High-Order Rotational Transition Probing and Slot-Array Couplers
Future ultra-broadband and low-latency radio access networks pose stringent specifications for time synchronizations. For 5G base stations, inter-site timing error should be <130ns for carrier aggregation and <10ns for h
ISSCC 2020
Session 29
RF & Wireless
A 660-to-676GHz 4×2 Oscillator-Radiator Array with Intrinsic Frequency-Filtering Feedback for Harmonic Power Boost Achieving 7.4dBm EIRP in 40nm CMOS
The THz region of the electromagnetic spectrum is gaining interest due to its unique spectroscopic properties that make it useful for gas detection, biological imaging, and accurate timekeeping. While several techniques
ISSCC 2020
Session 29
RF & Wireless
A 490GHz 32mW Fully Integrated CMOS Receiver Adopting Dual-Locking FLL
increasing demand for low-cost, low-power, and high-sensitivity THz receiver. Lately, heterodyne structures in CMOS technologies have been emerging as suitable solutions due to their advantages of low cost, high integrat
ISSCC 2020
Session 29
RF & Wireless
THzID: A 1.6mm2 Package-Less Cryptographic Identification Tag with Backscattering and Beam-Steering at 260GHz
Chiraag S. Juvekar2, Wanyeong Jung1, Rabia Tugce Yazicigil3, Anantha P. Chandrakasan1, Ruonan Han1 Massachusetts Institute of Technology, Cambridge, MA Analog Devices, Boston, MA 3 Boston University, Boston, MA 1 2 Energ
ISSCC 2020
Session 29
RF & Wireless
A 4×4 Distributed Multi-Layer Oscillator Network for Harmonic Injection and THz Beamforming with 14dBm EIRP at 416GHz in a Lensless 65nm CMOS IC
applications in communication, sensing, imaging, and spectroscopy [1]. However, due to the limited power-generation capability of a single source above the device fmax [2], efficient spatial power combining from multiple
ISSCC 2020
Session 3
Analog Circuits
An Integrated BAW Oscillator with <±30ppm Frequency
Danielle Griffith1, Ernest Ting-Ta Yen2, Kaichien Tsai1, Habeeb Ur Rahman Mohammed1, Baher Haroun1, Ali Kiaei2, Ahmad Bahai2 Texas Instruments, Dallas, TX; 2Texas Instruments, Santa Clara, CA 1 Wireless sensor nodes with
ISSCC 2020
Session 3
Analog Circuits
A 0.0088mm2 Resistor-Based Temperature Sensor Achieving 92fJ·K2 FoM in 65nm CMOS
University of Illinois, Urbana, IL Resistor-based temperature sensors can achieve superior performance in terms of energy efficiency and resolution compared to their BJT counterparts. Among them, Wien- (WB)[1]- and Wheat
ISSCC 2020
Session 3
Analog Circuits
A 0.51nW 32kHz Crystal Oscillator Achieving 2ppb Allan Deviation Floor Using High-Energy-to-Noise-Ratio Pulse Injection
minimum power while disturbing the oscillation as little as possible. In order to achieve subnW power consumption, there are three fundamental considerations: the loss in the crystal, the efficiency of energy injection,
ISSCC 2020
Session 3
Analog Circuits
A 16MHz CMOS RC Frequency Reference with ±400ppm Inaccuracy from -45°C to 85°C After Digital Linear Temperature Compensation
Systems-on-chip traditionally rely on bulky quartz crystals to comply with wired communication standards like CAN or USB 2.0. Integrated frequency references with better than 500ppm inaccuracy could meet this need, resul
ISSCC 2020
Session 3
Analog Circuits
A 34µW 32MHz RC Oscillator with ±530ppm Inaccuracy from -40°C to 85°C and 80ppm/V Supply Sensitivity Enabled by Pulse-Density Modulated Resistors
University of Illinois, Urbana, IL Monolithic frequency references built using on-chip time constants are gaining popularity as possible replacements to bulky quartz-crystal or MEMS-based oscillators in low-cost applicat
ISSCC 2020
Session 3
Analog Circuits
A CMOS Resistor-Based Temperature Sensor with a 10fJ∙K2 Resolution FoM and 0.4°C (3σ) Inaccuracy From −55°C to 125°C After a 1-point Trim
Energy efficiency and accuracy are important specifications of CMOS temperature sensors. BJT-based sensors achieve state-of-the-art accuracy [1], while Wheatstone-bridge (WhB) sensors achieve lower accuracy but state-of-
ISSCC 2020
Session 3
Analog Circuits
A 620µW BJT-Based Temperature-to-Digital Converter with 0.65mK Resolution and FoM of 190fJ·K2
(TDC) are used for temperature compensation of high-stability MEMS oscillators [1,2]. Such TDCs must achieve high resolution and high conversion rates in the kHz range to minimize temperature compensation impact on phase
ISSCC 2020
Session 3
Analog Circuits
A 23.6ppm/°C Monolithically Integrated GaN Reference Voltage Design with Temperature Range from -50°C to 200°C and Supply Voltage Range from 3.9 to 24V
Kai-Cheng Chung1, Neha Kumari1, Ke-Horng Chen1, Yin-Hsi Lin2, Shian-Ru Lin2, Tsung-Yen Tsai2, Ying-Zong Juang3 National Chiao Tung University, Hsinchu, Taiwan Realtek Semiconductor, Hsinchu, Taiwan 3 Taiwan Semiconductor
ISSCC 2020
Session 30
Wireless
A Temperature-Robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X-Band
Benton H. Calhoun, Steven M. Bowers University of Virginia, Charlottesville, VA To achieve the exponential growth needed for a 1-trillion-node Internet of Things (IoT) in the next decade, innovative solutions are require
ISSCC 2020
Session 30
Wireless
NB-IoT and GNSS All-in-One System-on-Chip Integrating
Low-Cost Solution Jongsoo Lee, Jaeyeol Han, Chilun Lo, Jongmi Lee, Wan Kim, Seungjin Kim, Byoungjoong Kang, Juyoung Han, Sangdon Jung, Takahiro Nomiyama, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang Samsung Electronics,
ISSCC 2020
Session 30
Wireless
A SAW-Less NB-IoT RF Transceiver with Hybrid Polar and On-Chip Switching PA Supporting Power Class 3 Multi-Tone Transmission
communication technology that benefits from the advantages of both cellular networks and narrowband transmission. Since the NB-IoT specification was finalized by 3GPP in 2016, several SoCs [1,2] and an RF transceiver [3]
ISSCC 2020
Session 30
Wireless
A 370µW 5.5dB-NF BLE/BT5.0/IEEE 802.15.4-Compliant Receiver with >63dB Adjacent Channel Rejection at >2 Channels Offset in 22nm FDSOI
Analog Devices, Cork, Ireland 1 2 Upcoming Internet-of-Things (IoT) applications require low-power multi-standard RF receiver (RX) front-ends. Interference rejection becomes increasingly important as ever more devices co
ISSCC 2020
Session 30
Wireless
A 0.5V BLE Transceiver with a 1.9mW RX Achieving -96.4dBm Sensitivity and 4.1dB Adjacent Channel Rejection at 1MHz Offset in 22nm FDSOI
Hironori Nakahara1, Norihito Suzuki1, Yutaka Nakada1, Yusuke Shinohe1, Shinichirou Etou1, Tetsuya Fujiwara2, Yasushi Katayama1 Sony Semiconductor Solutions, Atsugi, Japan Sony LSI Design, Atsugi, Japan 1 2 Towards the em
ISSCC 2020
Session 30
Wireless
A Crystal-Less BLE Transmitter with -86dBm FrequencyHopping Back-Channel WRX and Over-the-Air Clock Recovery from a GFSK-Modulated BLE Packet packet, meaning the TX LO is ready before the end of the ADV event. 8MHz also relaxes the required BPF center frequency and quality factor. Using two LOs allows for receiving and transmitting on different BLE channels and for optimizing each PLL controller.
Benton H. Calhoun2, David D. Wentzloff1 Figure 30.7.3 shows a simplified block diagram for both PLLs for reference recovery from the BLE packet and TX transmission. It is a type-I ADPLL with an embedded averaging process
ISSCC 2020
Session 30
Wireless
A 3.5mm×3.8mm Crystal-Less MICS Transceiver Featuring Coverages of ±160ppm Carrier Frequency Offset and 4.8-VSWR Antenna Impedance for Insertable Smart Pills
Gaurav Singh1, Peng Zhang1, Stefano Traferro1, Hannu Korpela1, Nick van Helleputte3, Robert Bogdan Staszewski2, Yao-Hong Liu1, Christian Bachmann1 imec-Netherlands, Eindhoven, The Netherlands University College Dublin, D
ISSCC 2020
Session 31
Digital Circuits
A 65nm 8.79TOPS/W 23.82mW Mixed-Signal OscillatorBased NeuroSLAM Accelerator for Applications in Edge Robotics
Simultaneous localization and mapping (SLAM) is a quintessential problem in cyber-physical systems with wide-spread applications in mobile robotics, selfdriving vehicles, AR, VR, etc. While computational methods [1] and
ISSCC 2020
Session 31
AI / ML
CIM-Spin: A 0.5-to-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems
*Equally-Credited Authors (ECAs) Annealing processors [1-3] based on the convergence property of the Ising model offer an attractive means for solving combinatorial optimization problems [4]. A recently developed anneali
ISSCC 2020
Session 31
Digital Circuits
A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators
Dynamic timing error detection and correction techniques, e.g. razor flops, have been previously applied to microprocessors to exploit the dynamic timing margin within pipelines [1]. Adaptive clock techniques have also b
ISSCC 2020
Session 32
Power Management
A 13.56MHz Current-Mode Wireless Power and Data Receiver with Efficient Power Extracting Controller and Energy-Shift Keying Technique for Loosely Coupled Implantable Devices Sung-Wan Hong
attractive solution. There are two types of WPT receivers (RXs), voltage-mode (VM) RX [1], [2] and current-mode (CM) RX [3], [4]. The VM-RX is suitable when the coupling coefficient (k12) between the transceiver (TX) and
ISSCC 2020
Session 32
Power Management
Self-Tunable Phase-Shifted SECE Piezoelectric EnergyHarvesting IC with a 30nW MPPT Achieving 446% Energy-Bandwidth Improvement and 94% Efficiency
extraction capability of piezoelectric energy harvesters (PEHs), the quality factor of mechanical resonators should be maximized over the extraction-energy frequency bandwidth (EFB). As a result, the EFB is often limited
ISSCC 2020
Session 32
Power Management
Electromagnetic Mechanical Energy-Harvester IC with No Off-Chip Component and One Switching Period MPPT Achieving up to 95.9% End-to-End Efficiency and 460% Energy-Extraction Gain
from sub-g vibrational environments while having a volume of a few cm3. Thus, such EMHs are promising candidates for powering net-zero-power sensor nodes as compared to their electrostatic- or piezoelectric-based counter