ISSCC 2021
Session 28
Medical & Bio
A 0.00378mm2 Scalable Neural Recording Front-End for Fully Immersible Neural Probes Based on a Two-Step Incremental Delta-Sigma Converter with Extended Counting and Hardware Reuse
of electronics into tissue-penetrating probes improves the signal quality and reduces parasitic effects for high-density recording of in vivo neural activity. In contrast to passive neural probes or devices implementing
ISSCC 2021
Session 28
Medical & Bio
Multi-Modal Peripheral Nerve Active Probe and Microstimulator with On-Chip Dual-Coil Power/Data Transmission and 64 2nd-Order Opamp-Less ΔΣ ADCs
Aly Shoukry, Camilo Tejeiro, Chenxi Tang, Enver Kilinc, Jaimin Joshi, Parisa Sabetian, Samantha Unger, José Zariffa, Paul Yoo, Roman Genov University of Toronto, Toronto, Canada The peripheral nervous system (PNS) enable
ISSCC 2021
Session 29
Digital Circuits
A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Computein-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification
memory-centric workloads (AI, graph-analytics) continue to gain momentum, technology solutions that provide higher on-die memory capacity/bandwidth can provide scalability beyond SRAM. Resistive RAM (RRAM) owing to (1) h
ISSCC 2021
Session 29
Digital Circuits
A 21×21 Dynamic-Precision Bit-Serial Computing Graph Accelerator for Solving Partial Differential Equations Using Finite Difference Method
now with University of California, Santa Barbara, CA 1 2 Partial differential equations (PDEs) are ubiquitous in physics and engineering and used for understanding various physical phenomena, including heat, diffusion, f
ISSCC 2021
Session 29
Digital Circuits
80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with SelfReferenced Asynchronous Adaptive Droop Mitigation
4-to-6.5GHz Frequency Locked Loop (FLL) implemented in 10nm CMOS, targeting high performance SoCs that require uninterrupted, overshoot-free clocks for Dynamic Voltage and Frequency Scaling (DVFS). The FLL supports gradu
ISSCC 2021
Session 29
Digital Circuits
A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur
Inphi, Santa Clara, CA 1 2 Ring oscillator (RO)-based frequency synthesizers enable cost-efficient and scalingfriendly implementation, but also result in worse phase noise compared to LC-based alternatives. There has bee
ISSCC 2021
Session 29
Digital Circuits
A 0.008mm2 1.5mW 0.625-to-200MHz Fractional Output Divider with 120fsrms Jitter Based on Replica-DTC-Free Background Calibration
A compact, low-power, low-jitter clock system supporting multiple output frequencies is required in many applications. Using several PLLs to generate multiple frequencies consumes large power and chip area [1]. Alternati
ISSCC 2021
Session 29
Digital Circuits
A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOS
microprocessors for applications such as HPC and AI, the available power is strictly limited by the thermal power budget. To overcome this limitation, recently, each core has been implemented with a dedicated integrated
ISSCC 2021
Session 29
Digital Circuits
A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS
University of Washington, Seattle, WA Single-inductor multiple-output (SIMO) converters present a promising technology for enabling fine-grained supply-voltage (Vdd) domains in SoCs. With efficiencies approaching those o
ISSCC 2021
Session 29
Digital Circuits
115nA@3V ULPMark-CP Score 1205 SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU
applications require ultra-low power consumption. In a conventional design, most modules except the crystal oscillator (XO32), real-time clock (RTC), and retention memory are turned off to reduce the current in sleep sta
ISSCC 2021
Session 3
Digital Processors
XBOX Series X: A Next-Generation Gaming Console SoC
improvement over the prior generation with up to 2× GPU performance, 3× CPU performance, 2.4× GPU performance/W, 1.7× memory bandwidth and 2× IO bandwidth to feed the additional processing capability and features shown i
ISSCC 2021
Session 3
Digital Processors
The A100 Datacenter GPU and Ampere Architecture
Nvidia, Santa Clara, CA The diversity of compute-intensive applications in modern cloud data centers has driven the explosion of GPU-accelerated cloud computing. Such applications include AI deep learning training and in
ISSCC 2021
Session 3
Digital Processors
Kunlun: A 14nm High-Performance AI Processor for Diversified Workloads
In order to be able to handle a wide range of AI applications, such as for speech, image, language and autonomous driving, it is necessary that an AI accelerator be flexible enough to handle diversified workloads. Baidu
ISSCC 2021
Session 30
Memory
A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture
Hyunsoo Lee, Sungmook Lim, Sun-Young Jung, Hyeongjin Choi, Taikyu Kang, Gwan Park, Chul-Woo Yang, Jeong-Gil Choi, Gwihan Ko, Jaehyeon Shin, Ingon Yang, Junghoon Nam, Hyeokchan Sohn, Seok-In Hong, Yohan Jeong, Sung-Wook C
ISSCC 2021
Session 30
Memory
A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm2 Bit Density
Kristopher H. Gaewsky2, Chang Wan Ha1, Rezaul Haque2, Owen W. Jungroth2, Steven Law1, Aliasgar S. Madraswala2, Binh Ngo2, Naveen Prabhu V2, Shantanu Rajwade1, Karthikeyan Ramamurthi2, Rohit S. Shenoy1, Jacqueline Snyder2
ISSCC 2021
Session 30
Memory
A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface
Bong-Kil Jung, Jaedoeg Lyu, Hogil Lee, Won-Tae Kim, Hongsoo Jeon, Sunghoon Kim, In-Mo Kim, Jae-Ick Son, Kyoungtae Kang, Sang-Won Shim, JongChul Park, Eungsuk Lee, Kyung-Min Kang, Sang-Won Park, Jaeyun Lee, Seung Hyun Moo
ISSCC 2021
Session 30
Memory
A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology
Mitsuhiro Abe1, Teruo Takagiwa1, Yuki Shimizu1, Junji Musha1, Katsuaki Sakurai1, Jumpei Sato1, Tetsuaki Utsumi1, Kazuhide Yoneya1, Yasuhiro Suematsu1, Toshifumi Hashimoto1, Takeshi Hioka1, Kosuke Yanagidaira1, Masatsugu
ISSCC 2021
Session 31
Analog Circuits
An 82mW ΔΣ-Based Filter-Less Class-D Headphone Amplifier with -93dB THD+N, 113dB SNR and 93% Efficiency
(ANC) headphones require low-latency digital-input headphone drivers that consume the lowest possible power to maximize battery life while providing high-fidelity audio playback. Typical headphone drivers use Class-A/AB
ISSCC 2021
Session 31
Analog Circuits
A 0.9V 28MHz Dual-RC Frequency Reference with 5pJ/Cycle and ±200ppm Inaccuracy from -40°C to 85°C
applications require a stable on-chip frequency reference with low energy (<10pJ/cycle) and high frequency stability (below ±300ppm). CMOS RC frequency references are promising due to their low-cost integration and high
ISSCC 2021
Session 31
Analog Circuits
A 0.14mm2 16MHz CMOS RC Frequency Reference with a 1-Point Trimmed Inaccuracy of ±400ppm from −45°C to 85°C
Recently, rapid strides have been made in improving the accuracy of RC-based frequency references [1-3]. Inaccuracies better than ±500ppm from -45°C to 85°C have been achieved, but typically at the expense of a costly an
ISSCC 2021
Session 31
Analog Circuits
A Chopper-Stabilized Amplifier with -107dB IMD and 28dB Suppression of Chopper-Induced IMD
low-frequency noise. However, the interaction between the input signal and the chopper clock can cause chopper-induced intermodulation distortion (IMD) [1-5]. This is especially problematic for input frequencies (Fin) ne
ISSCC 2021
Session 32
Clocking & PLLs
A 365fsrms-Jitter and −63dBc-Fractional Spur 5.3GHz-RingDCO-Based Fractional-N DPLL Using a DTC Second/ThirdOrder Nonlinearity Cancelation and a Probability-DensityShaping ΔΣM
data-rates by combining more carrier components, 5G RF transceivers require many carrier frequencies, resulting in the situation of many LC PLLs occupying a large silicon area. Ring-oscillator-based digital PLLs (RO-DPLL
ISSCC 2021
Session 32
Clocking & PLLs
A 14nm Analog Sampling Fractional-N PLL with a Digital-toTime Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels
requires sub-100fs rms jitter to support 64-QAM and 2×2 MIMO under non-ideal channel conditions [1]. Although fractional-N phaselocked loops (PLLs) employing digital-to-time converters (DTCs) and sampling phase detectors
ISSCC 2021
Session 32
Clocking & PLLs
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter
Francesco Buccoleri1, Luca Avallone2, Angelo Parisi1, Andrea Leonardo Lacaita1, Michael Peter Kennedy2, Carlo Samori1, Salvatore Levantino1 Politecnico di Milano, Milan, Italy University College Dublin, Dublin, Ireland f
ISSCC 2021
Session 32
Clocking & PLLs
A 104fsrms-Jitter and −61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique
2 *Equally Credited Authors (ECAs) Subsampling PLLs (SSPLLs) are attractive architectures to generate ultra-low-jitter RF signals due to their intrinsically high phase-error-detection gain, KSH. However, this highgain op
ISSCC 2021
Session 32
Clocking & PLLs
A 24GHz Self-Calibrated ADPLL-Based FMCW Synthesizer with 0.01% rms Frequency Error Under 3.2GHz Chirp Bandwidth and 320MHz/µs Slope
for millimeter-wave (mm-wave) frequency-modulated continuous-wave (FMCW) radars. Large-chirp-bandwidth (BWchirp) sawtooth waveforms are required to be synthesized with fast slope and high-frequency linearity for accurate
ISSCC 2021
Session 32
Clocking & PLLs
A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS
Sergey Bershansky2, Nir Geron2, Ashoke Ravi3, Rotem Banin2, Jasmin Kadry2, Gil Horovitz2, Christian Krassnitzer1, Christoph Duller1, Patrick Torta1, Mark Elzinga4, Kamran Azadet5 Intel, Villach, Austria Intel, Israel, Is
ISSCC 2021
Session 32
Clocking & PLLs
A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth
independent crystal oscillators (XOs): a 32.768kHz XO for the real-time clock (RTC) and a tens of MHz XO for low-jitter clock and carrier synthesis. To reduce the number of XOs, 32kHz-reference phase-locked loops (PLLs)
ISSCC 2021
Session 32
Clocking & PLLs
A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays
Francesco Buccoleri1, Luca Avallone2, Angelo Parisi1, Dmytro Cherniak3, Andrea L. Lacaita1, Michael Peter Kennedy2, Carlo Samori1, Salvatore Levantino1 Politecnico di Milano, Milano, Italy University College Dublin, Dubl
ISSCC 2021
Session 33
Wireless
A Fully Integrated GaN-on-Silicon Gate Driver and GaN Switch with Temperature-compensated Fast Turn-on Technique for Improving Reliability
Gallium-Nitride (GaN) high-electron-mobility transistors (HEMTs) have the advantages of low parasitic capacitance, low on-resistance (RON), and no reverse recovery charge loss [1-5]. Thus, using GaN HEMTs one can optimiz
ISSCC 2021
Session 33
Wireless
A 600V GaN Active Gate Driver with Dynamic Feedback Delay Compensation Technique Achieving 22.5% Turn-On Energy Saving are shown in Fig. 33.2.3. The detection branch current Isen is copied to the AMPD proportionally through current mirror pairs of MP5 and MP6. For large dv/dt value, the gate voltage of MP0 is higher, realizing lower gate overdrive voltage. Otherwise the gate overdrive voltage will increase to enable a larger driving current.
The phase modulation circuit and its waveforms are depicted in Fig. 33.2.3. The phase difference between SRstart and VFBD is detected by the phase-detect circuit (PD) and then converted to voltage domain through the char
ISSCC 2021
Session 33
Wireless
An Automotive-Use 2MHz 100VOUT Flicker-Free FrequencyModulated GaN-Based Buck-Boost LED Driver Achieving Bootstrap Charge Balancing and 16.8dBµV Radiated EMI Noise Reduction
(up to 30 LEDs in series) for sequential turn signal light. As the LEDs are turned on/off sequentially, the output voltage across the LED string (VOUT) can be below, equal to, or above the input battery voltage (VIN) whi
ISSCC 2021
Session 33
Wireless
An 8A 998A/inch3 90.2% Peak Efficiency 48V-to-1V DC-DC Converter Adopting On-Chip Switch and GaN Hybrid Power Conversion
intelligent and power hungry. The 48V-to-1V converter, which offers a promising solution to the highpower density data center and automotive applications, is quickly gaining the interest of researchers [1-4]. The prior s
ISSCC 2021
Session 33
AI / ML
A 1.25W 46.5%-Peak-Efficiency Transformer-in-Package Isolated DC-DC Converter Using Glass-Based Fan-Out Wafer-Level Packaging Achieving 50mW/mm2 Power Density polyimide layers with a dielectric breakdown strength of >400V/μm are laminated among 3 RDLs to form isolation barriers, providing better than 5kV isolation rating. Consequently, the transformer achieves a coupling coefficient of 0.8, enabling over 1W power delivery.
Daquan Yu2, Ming Liu3, Lin Cheng1 Figure 33.5.3 shows the simplified schematic of the power stage. In the Tx, an LC tank oscillator with an AC-coupled structure is adopted. To handle a wide supply voltage (VDD) range of
ISSCC 2021
Session 33
Wireless
A Wireless Power Transfer System with Up-to-20% LightLoad Efficiency Enhancement and Instant Dynamic Response by Fully Integrated Wireless Hysteretic Control for Bioimplants
Wireless power transfer (WPT) systems are becoming increasingly popular for sub100mW biomedical applications [1-5]. Because the received power is sensitive to coupling and loading conditions, power/voltage regulations ar
ISSCC 2021
Session 33
Wireless
A Frequency-Splitting-Based Wireless Power and Data Transfer IC for Neural Prostheses with Simultaneous 115mW Power and 2.5Mb/s Forward Data Delivery
electrical cochlear implants (CIs) have given >500,000 patients worldwide a better life to date. However, the electrical neural stimulation has limited spatial resolution due to the spread of stimulation current, which r
ISSCC 2021
Session 33
Wireless
A Decentralized Daisy-Chain-Controlled Switched-Capacitor Driver for Microrobotic Actuators with 10× Power-Reduction Factor and Over 300V Drive Voltage
Electrostatic and piezoelectric actuators are used in a number of mm- and cm-scale robotic applications due to their relatively high energy-density at small size and weight [1-3]. Such transducers typically require high
ISSCC 2021
Session 33
Wireless
A Hybrid Switching Supply Modulator Achieving 130MHz Envelope-Tracking Bandwidth and 10W Output Power for 2G/3G/LTE/NR RF Power Amplifiers
Young-Ho Jung, Jaeyeol Han, Ik-Hwan Kim, Sung-Youb Jung, Takahiro Nomiyama, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho Samsung Electronics, Hwasung, Korea Envelope tracking (ET) is a key technology improving efficien
ISSCC 2021
Session 34
Image Sensors
An 8960-Element Ultrasound-on-Chip for Point-of-Care Ultrasound
Sewook Hwang1, Joseph Lutsky1, Jungwook Yang1, Liewei Bao1, Leung Kin Chiu1, Graham Peyton1, Hamid Soleimani1, Bob Ryan1, J. R. Petrus1, Youn-Jae Kook1, Tyler S. Ralston2, Keith G. Fife2, Jonathan M. Rothberg2 Butterfly
ISSCC 2021
Session 34
Image Sensors
A 21pJ/frame/pixel Imager and 34pJ/frame/pixel Image Processor for a Low-Vision Augmented-Reality Smart Contact Lens the duration of Φ1 in 4- and 6-bit modes while still meeting the PGA settling accuracy. The ADC sampling capacitor array embeds an analog offset subtraction technique to calibrate accumulated offset errors and adjust the pixel black level prior to signal quantization.
Figure 34.2.3 shows the imager characterization results. The core imager energy consumption per frame remains relatively flat across a wide range of frame rates. This is achieved by powering down the imager during idle p
ISSCC 2021
Session 34
Image Sensors
A 32×32 Pixel 0.46-to-0.75THz Light-Field Camera SoC in 0.13µm CMOS
Robin Zatta, Ullrich R. Pfeiffer University of Wuppertal, Wuppertal, Germany Light-field (LF) refers to the spatio-directional light flow in space. In LF imaging, light rays are recorded along different positions and dir
ISSCC 2021
Session 34
Image Sensors
An Energy-Replenishing Ultrasound Pulser with 0.25CV2f Dynamic Power Consumption
Daegu Catholic University Medical Center, Daegu, Korea 4 Daegu Gyeongbuk Institute of Science and Technology, Daegu, Korea 5 New York University Abu Dhabi, Abu Dhabi, United Arab Emirates leads to the end of Φ1 by turnin
ISSCC 2021
Session 35
Digital Circuits
An Octa-Core 2.8/2GHz Dual-Gear Sensor-Assisted High-Speed and Power-Efficient CPU in 7nm FinFET 5G Smartphone SoC
Chi-Hsun Chiang, Yi-Hsuan Lin, Wen-Wen Hsieh, Barry Chen, Yi-Chang Zhuang, Cheng-Yuh Wu, Jia-Ming Chen, YS Chen, Cheng-Tien Wan, Ericbill Wang, Alex Chiou, Ping Kao, Yuwen Tsai, Harry H. Chen, Shih-Arn Hwang MediaTek, Hs
ISSCC 2021
Session 35
Digital Circuits
A 0.021mm2 PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FDSOI Technology
Sébastien Genevey1, Lionel Pierrefeu1, Emmanuel Grand1, Joerg Winkler3, Jonathan Park4, Gaël Pillonnet2, Vincent Huard1, Andrea Bonzo1, Philippe Flatresse1 Dolphin Design, Meylan, France CEA-Léti, Grenoble, France 3 Glob
ISSCC 2021
Session 35
Digital Circuits
Thread-Level Power Management for a Current- and Temperature-Limiting System in a 7nm HexagonTM Processor
Qualcomm, Raleigh, NC 1 2 The Hexagon™ compute DSP (CDSP) integrates a master VLIW scalar processor and a slave vector coprocessor to enable high-performance and energy-efficient computing for multimedia, voice, audio, v
ISSCC 2021
Session 36
Hardware Security
Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security including PUF responses lying at bin boundaries (affecting masking only marginally, see BER below).
In Fig. 36.1.4, the TRNG was confirmed to have consistent measured output quality across very different data patterns (all 0’s for minimum jitter vs. random data), 0.8-to-1V supply and -10 to 75°C temperature. The min-en
ISSCC 2021
Session 36
Hardware Security
An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local Feedback and Global Switched-Mode Control
side-channel information in the form of correlated power and electromagnetic (EM) signals, leading to physical sidechannel analysis (SCA) attacks. Circuit-level countermeasures against power/EM SCA include current equali
ISSCC 2021
Session 36
Hardware Security
A Modeling Attack Resilient Strong PUF with Feedback-SPN Structure Having <0.73% Bit Error Rate Through In-Cell Hot-Carrier Injection Burn-In
lowenergy and low-latency authentication requirements of IoT applications, owing to their exponential number of challenge-response pairs (CRPs). However, Strong PUFs suffer from vulnerability to modeling attacks and a hi
ISSCC 2021
Session 36
Hardware Security
A Physically Unclonable Function Combining a Process Mismatch Amplifier in an Oscillator Collapse Topology
Physically unclonable functions (PUFs) have been actively investigated as a promising solution for low-cost secure authentication in Internet of Things (IoT) applications. A PUF should generate unique challenge-response
ISSCC 2021
Session 36
Hardware Security
An Automatic Self-Checking and Healing Physically Unclonable Function (PUF) with <3×10-8 Bit Error Rate
*Equally Credited Authors (ECAs) Physically unclonable functions (PUF) have emerged as a promising solution for secure and low-cost key storage and hardware authentication. A key challenge in PUF designs is ensuring the