ISSCC 2021

2021

195 篇论文 · Wireline I/O (20) · RF & Wireless (18) · mm-Wave (17) · Digital Processors (16) · Data Converters (14)

ISSCC 2021 Session 4 Digital Processors
A 7nm 5G Mobile SoC Featuring a 3.0GHz Tri-Gear Application Processor Subsystem
Hsinchen Chen1, Rolf Lagerquist1, Ashish Nayak1, Hugh Mair1,
Gokulakrishnan Manoharan1, Ericbill Wang2, Gordon Gammie1, Efron Ho1, Anand Rajagopalan1, Lee-Kee Yong1, Ramu Madhavaram1, Madhur Jagota1, Chi-Jui Chung1, Sudhakar Maruthi1, Jenny Wiedemeier1, Tao Chen1, Henry Hsieh2, Da
ISSCC 2021 Session 4 Digital Processors
An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET
Colin Schmidt*, John Wright*, Zhongkai Wang, Eric Chang, Albert Ou,
such as deep neural networks (DNNs), increasingly rely on dense arithmetic compute patterns that are ill-suited for general-purpose processors, leading to a rise in domain-specific compute accelerators [1]. Many of these
Woorham Bae, Sean Huang, Anita Flynn, Brian Richards, Krste Asanović,
ISSCC 2021 Session 4 Digital Processors
A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7µW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
Davide Rossi1, Francesco Conti1, Manuel Eggiman2, Stefan Mach2,
Alfio Di Mauro2, Marco Guermandi1,3, Giuseppe Tagliavini1, Antonio Pullini2,3, Igor Loi3, Jie Chen1,3, Eric Flamand2,3, Luca Benini1,2 University of Bologna, Bologna, Italy ETH Zurich, Zurich, Switzerland 3 Greenwaves Te
ISSCC 2021 Session 4 Digital Processors
BioAIP: A Reconfigurable Biomedical AI Processor with Adaptive Learning for Versatile Intelligent Health Monitoring
Jiahao Liu, Zhen Zhu, Yong Zhou, Ning Wang, Guanghai Dai, Qingsong Liu,
health monitoring devices automatically detect abnormalities in users’ biomedical signals (e.g. arrhythmia from an ECG signal or a seizure from an EEG signal) through signal classification. Compared to conventional machi
Jianbiao Xiao, Yuxiang Xie, Zirui Zhong, Hongduo Liu, Liang Chang, Jun
ISSCC 2021 Session 4 Digital Processors
A 144Kb Annealing System Composed of 9×16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems
Takashi Takemoto1, Kasho Yamamoto2, Chihiro Yoshimura2, Masato Hayashi2,
Service, Sapporo, Japan 1 2 Substantial progress has been made on a new computer architecture, known as an annealing processor (AP) [1–4]. The AP can effectively solve NP-hard combinatorial optimization problems by provi
Masafumi Tada3, Hiroaki Saito4, Mayumi Mashimo2, Masanao Yamaoka2 Hita
ISSCC 2021 Session 4 Digital Processors
A 91mW 90fps Super-Resolution Processor for Full HD Images
Hsueh-Yen Shen, Yu-Chi Lee, Tzu-Wei Tong, Chia-Hsiang Yang
Super resolution is the process of reconstructing a high-resolution (HR) image from a low-resolution (LR) one. Super-resolution technology enables high-resolution video streaming, image zoom-in, and far object recognitio
National Taiwan University, Taipei, Taiwan
ISSCC 2021 Session 4 Digital Processors
An Area and Energy Efficient 0.12nJ/Pixel 8K 30fps AV1 Video Decoder in 5nm CMOS Process
Tae Sung Kim, Seokhyun Lee, Kyungkoo Lee, Sunyoung Shin,
SeungSick Jun, YongMi Lee, Seungyong Lee, Homin Kang, Changhyun Yim, Yohan Lim, Eikyung Moon, Sukhwan Lim, Kyungah Jeong, Inyup Kang Samsung Electronics, Hwaseong, Korea Major content providers such as YouTube and Netfli
ISSCC 2021 Session 5 Analog Circuits
A 1.5µW 0.135pJ∙%RH2 CMOS Humidity Sensor Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array
Heyi Li1, Zhichao Tan2, Yuanxin Bao3, Han Xiao3, Hao Zhang1, Kaixuan Du1,
China in the DSM is ~200fF, and an LSB of the SAR DAC is ~50fF. Hence, the differential input range of the DSM can be calculated as 2%200fF/50fF = 8LSBs of the SAR, and 0.5LSB error is equal to 6.25% of the range. When A
Yihan Zhang1, Le Ye1,3, Ru Huang1 Peking University, Beijing, China Zh
ISSCC 2021 Session 5 Analog Circuits
Capacitance-to-Digital Converter for Operation Under
Uncertain Harvested Voltage down to 0.3V with No Trimming, Reference and Voltage Regulation
capacitive sensing via capacitance-to-digital conversion (CDC) needs to operate with minimal or no support from additional circuitry such as voltage regulation, voltage/current references or digital post-processing as sh
Orazio Aiello1, Paolo Crovetti2, Massimo Alioto1 National University o
ISSCC 2021 Session 5 Analog Circuits
A Highly Digital 2210µm2 Resistor-Based Temperature Sensor with a 1-Point Trimmed Inaccuracy of ±1.3°C (3σ) from -55°C to 125°C in 65nm CMOS
Jan A. Angevare1, Youngcheol Chae2, Kofi A. A. Makinwa1
Yonsei University, Seoul, Korea 1 2 Microprocessors and SoCs employ multiple temperature sensors to prevent overheating and ensure reliable operation. Such sensors should be small (<10,000µm)) to monitor local hot-spots
Delft University of Technology, Delft, The Netherlands
ISSCC 2021 Session 5 Analog Circuits
A Hybrid Thermal-Diffusivity/Resistor-Based Temperature Sensor with a Self-Calibrated Inaccuracy of ±0.25°C (3σ) from −55°C to 125°C
Sining Pan, Jan A. Angevare, Kofi A. A. Makinwa
Resistor-based temperature sensors can achieve higher resolution and energy-efficiency than traditional BJT-based sensors. To reach similar accuracy, however, they typically require 2-point (2-pt) calibration, compared t
Delft University of Technology, Delft, The Netherlands
ISSCC 2021 Session 5 Analog Circuits
A 770 kS/s Duty-Cycled Integrated-Fluxgate Magnetometer for Contactless Current Sensing
Preetinder Garcha1,2, Viola Schaffer3, Baher Haroun1, Srinath Ramaswamy1,
Instruments, Freising, Germany 4 Kilby Labs, Texas Instruments, Santa Clara, CA 1 2 Electric vehicle battery chargers, solar-panel inverters, industrial power monitoring, and many other high voltage applications rely on
Jim Wieser4, Jeffrey Lang2, Anantha Chandrakasan2 Kilby Labs, Texas In
ISSCC 2021 Session 5 Analog Circuits
A MEMS Coriolis Mass Flow Sensor with 300µg/h/√Hz Resolution and ±0.8mg/h Zero Stability
Arthur C. de Oliveira1, Jarno Groenesteijn2, Remco J. Wiegerink3, Kofi A. A. Makinwa1
in the pharmaceutical, food, and semiconductor industries to measure small amounts (<1gram/hour) of liquids and gases. MEMS thermal flow sensors currently achieve state-of-the-art performance in terms of resolution, size
Delft University of Technology, Delft, The Netherlands Bronkhorst BV,
ISSCC 2021 Session 5 Analog Circuits
A 5V Dynamic Class-C Paralleled Single-Stage Amplifier with Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting Technique
Seok-Tae Koh, Ji-Hun Lee, Gyeong-Gu Kang, Hyunki Han, Hyun-Sik Kim
One of the most key analog blocks in VLSI is probably the buffer amplifier dedicated to driving large off-chip loads. However, achieving fast settling-time and high output current drivability over a wide input voltage ra
KAIST, Daejeon, Korea
ISSCC 2021 Session 6 RF & Wireless
A Low-Power and Low-Cost 14nm FinFET RFIC Supporting Legacy Cellular and 5G FR1
Jongsoo Lee, Byoungjoong Kang, Seongwon Joo, Seokwon Lee, Joongho Lee,
Seunghoon Kang, Ikkyun Jo, Suseop Ahn, Jaeseung Lee, Jeongyeol Bae, Won Ko, Wonjun Jung, Sangho Lee, Sangsung Lee, Euiyoung Park, Sungjun Lee, Jeongkyun Woo, Jaehoon Lee, Yanghoon Lee, Kyungmin Lee, Jongwoo Lee, Thomas B
ISSCC 2021 Session 6 RF & Wireless
A 4-Way Doherty Digital Transmitter Featuring 50%-LO Signed IQ Interleave Upconversion with more than 27dBm Peak Power and 40% Drain Efficiency at 10dB Power BackOff Operating in the 5GHz Band
Mohammadreza Beikmirza1, Yiyu Shen1,2, Mohammadreza Mehrpoo1,3,
Mohsen Hashemi1,4, Dieuwert Mul1, Leo C.N. de Vreede1, Morteza S. Alavi1 Delft University of Technology, Delft, The Netherlands now with imec-Netherlands, Eindhoven, The Netherlands 3 now with Broadcom-Netherlands, Bunni
ISSCC 2021 Session 6 RF & Wireless
A 0.9V Dual-Channel Filtering-by-Aliasing Receiver Front-End Achieving +35dBm IIP3 and <−81dBm LO Leakage Supporting Intra- and Inter-Band Carrier Aggregation
Shi Bu, Sudhakar Pamarti
Programmable receivers have drawn a lot of attention in recent years, especially those exploiting periodically time-varying (PTV) circuits. N-path filters and mixer-first receivers [1$3] achieve sharp filtering and good
University of California, Los Angeles, CA
ISSCC 2021 Session 6 RF & Wireless
A 3dB-NF 160MHz-RF-BW Blocker-Tolerant Receiver with Third-Order Filtering for 5G NR Applications
Mohammad Ali Montazerolghaem1, Sergio Pires2, Leo C.N. de Vreede1, Masoud Babaie1
imposed several challenges in the design of sub-6GHz receivers (RX). Firstly, the maximum channel bandwidth (2BW) increases to 100MHz, while a -15dBm continuous-wave (CW) blocker can be located only Δf=85MHz away from th
Delft University of Technology, Delft, The Netherlands Ampleon, Nijmeg
ISSCC 2021 Session 6 RF & Wireless
Full-Duplex Receiver with Wideband Multi-Domain FIR
Cancellation Based on Stacked-Capacitor, N-Path SwitchedCapacitor Delay Lines Achieving >54dB SIC Across 80MHz, BW and >
Aravind Nagulu*1, Sasank Garikapati*1, Mostafa Essawy2, Igor Kadota1, Tingjun Chen1, Arun Natarajan2, Gil Zussman1, Harish Krishnaswamy1 Columbia University, New York, NY Oregon State University, Corvallis, OR 1 2 *Equal
ISSCC 2021 Session 6 AI / ML
A 1.75dB-NF 25mW 5GHz Transformer-Based NoiseCancelling CMOS Receiver Front-End
Kaituo Yang1, Chirn Chye Boon1, Guangyin Feng2, Chenyang Li1, Zhe Liu1,
Massachusetts Institute of Technology, Cambridge, MA 1 2 With continuous exploitation of sub-6GHz wireless communication standards and the advent of 5G and 6G, the demand for faster speed and wider coverage keeps evolvin
Ting Guo1, Xiang Yi3, Yangtao Dong1, Ao Zhou1, Xiaoying Wang1 Nanyang
ISSCC 2021 Session 7 Image Sensors
A 4-tap 3.5µm 1.2Mpixel Indirect Time-of-Flight CMOS Image Sensor with Peak Current Mitigation and Multi-User Interference Cancellation
Min-Sun Keel, Daeyun Kim, Yeomyung Kim, Myunghan Bae, Myoungoh Ki,
Bumsik Chung, Sooho Son, Hoyong Lee, Heeyoung Jo, Seung-Chul Shin, Sunjoo Hong, Jaeil An, Yonghun Kwon, Sungyoung Seo, Sunghyuck Cho, Youngchan Kim, Young-Gu Jin, Youngsun Oh, Yitae Kim, JungChak Ahn, Kyoungmin Koh, Yong
ISSCC 2021 Session 7 Image Sensors
A 48×40 13.5mm Depth Resolution Flash LiDAR Sensor with In-Pixel Zoom Histogramming Time-to-Digital Converter
Bumjun Kim1, Seonghyeok Park1, Jung-Hoon Chun2,3, Jaehyuk Choi2,3, Seong-Jin Kim1
diverse applications such as user identification, interactive user interfaces with AR/VR devices, and self-driving cars. Direct time-of-flight (D-ToF) systems, LiDAR sensors, are desirable for long-distance measurements
Ulsan National Institute of Science and Technology, Ulsan, Korea Sungk
ISSCC 2021 Session 7 Image Sensors
A 189×600 Back-Illuminated Stacked SPAD Direct Time-of-Flight Depth Sensor for Automotive LiDAR Systems
Oichi Kumagai1, Junichi Ohmachi1, Masao Matsumura1, Shinichiro Yagi1,
Kenichi Tayu1, Keitaro Amagawa2, Tomohiro Matsukawa1, Osamu Ozawa1, Daisuke Hirono1, Yasuhiro Shinozuka1, Ryutaro Homma1, Kumiko Mahara2, Toshio Ohyama1, Yousuke Morita1, Shohei Shimada1, Takahisa Ueno3, Akira Matsumoto1
ISSCC 2021 Session 7 Image Sensors
A 256×128 3D-Stacked (45nm) SPAD FLASH LiDAR with 7-Level Coincidence Detection and Progressive Gating for 100m Range and 10klux Background Light
Preethi Padmanabhan1, Chao Zhang2, Marco Cazzaniga3, Baris Efe1,
Augusto R. Ximenes4, Myung-Jae Lee5, Edoardo Charbon1 EPFL, Neuchâtel, Switzerland ADAPS Photonics, Shenzhen, China 3 Intuitive Surgical, Aubonne, Switzerland 4 Facebook, Redmond, WA 5 Korea Institute of Science and Tech
ISSCC 2021 Session 7 Image Sensors
A 250fps 124dB Dynamic-Range SPAD Image Sensor Stacked with Pixel-Parallel Photon Counter Employing Sub-Frame Extrapolating Architecture for Motion Artifact Suppression
Jun Ogi1, Takafumi Takatsuka1, Kazuki Hizu1, Yutaka Inaoka1, Hongbo Zhu1,
Yasuhisa Tochigi1, Yoshiaki Tashiro1, Fumiaki Sano1, Yusuke Murakawa2, Makoto Nakamura2, Yusuke Oike1 Sony Semiconductor Solutions, Kanagawa, Japan Sony Semiconductor Manufacturing, Nagasaki, Japan 1 2 Photon-count imagi
ISSCC 2021 Session 7 Image Sensors
A High-Speed Back-Illuminated Stacked CMOS Image Sensor with Column-Parallel kT/C-Cancelling S&H and Delta-Sigma ADC
Chihiro Okada1, Koushi Uemura1, Luong Hung1, Kouji Matsuura1,
Takashi Moue1, Daisuke Yamazaki1, Kazutoshi Kodama1, Masafumi Okano1, Takafumi Morikawa1, Kazuyoshi Yamashita1, Osamu Oka2, Itai Shvartz3, Golan Zeituni3, Ariel Benshem3, Noam Eshel3, Yoshiaki Inada1 Sony Semiconductor S
ISSCC 2021 Session 7 Image Sensors
A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest Detection
Martin Lefebvre, Ludovic Moreau, Rémi Dekimpe, David Bol
Mixed-signal vision chips are becoming increasingly popular for low-power embedded computer vision applications on smartphones, wearables and IoT nodes, as they meet stringent power and area constraints while maintaining
Université catholique de Louvain, Louvain-la-Neuve, Belgium
ISSCC 2021 Session 7 Image Sensors
A 1-inch 17Mpixel 1000fps Block-Controlled Coded-Exposure Back-Illuminated Stacked CMOS Image Sensor for Computational Imaging and Adaptive Dynamic Range Control
Tomoki Hirata, Hironobu Murata, Hideaki Matsuda, Yojiro Tezuka, Shiro Tsunai
In recent developments, image sensors are no longer simply a means for collecting optical signals, but rather, are increasingly expected to serve as intelligent systems with surrounding configurations. Coded exposure (CE
Nikon, Tokyo, Japan
ISSCC 2021 Session 7 Image Sensors
1/2.74-inch 32Mpixel-Prototype CMOS Image Sensor with 0.64µm Unit Pixels Separated by Full-Depth Deep-Trench Isolation
JongEun Park, Sungbong Park, Kwansik Cho, Taehun Lee, Changkyu Lee,
DongHyun Kim, Beomsuk Lee, SungIn Kim, Ho-Chul Ji, DongMo Im, Haeyong Park, Jinyoung Kim, JungHo Cha, Taehoon Kim, In-Sung Joe, Soojin Hong, Chongkwang Chang, Jingyun Kim, WooGwan Shim, Taehee Kim, Jamie Lee, Donghyuk Pa
ISSCC 2021 Session 8 Wireline I/O
A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS
Jihwan Kim*1, Sandipan Kundu*1, Ajay Balankutty1, Matthew Beach2,
Bong Chan Kim1, Stephen Kim1, Yutao Liu1, Savyassachi Keshava Murthy1, Priya Wali1, Kai Yu1, Hyung Seok Kim1, Chuan-chang Liu1, Dongseok Shin1, Ariel Cohen3, Yongping Fan1, Frank O’Mahony1 Intel, Hillsboro, OR Foundation
ISSCC 2021 Session 8 Wireline I/O
An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS
Minsoo Choi*1, Zhongkai Wang*1, Kyoungtae Lee1, Kwanseo Park1,
for ultra-high-speed interconnects has driven the development of wireline TXs operating at >100Gb/s per lane [1-4]. This paper presents a PAM-4 TX achieving 200Gb/s with improved output bandwidth and output swing by mini
Zhaokai Liu1, Ayan Biswas1, Jaeduk Han2, Elad Alon1 University of Cali
ISSCC 2021 Session 8 Wireline I/O
An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7nm CMOS
Marcel A. Kossel1, Vishal Khatri1,4, Matthias Braendli1, Pier Andrea Francese1,
Thomas Morf1, Serdar A. Yonar1, Mridula Prathapan1, Eric J. Lukes2, Raymond A. Richetta2, Carrie Cox3 IBM Research, Rüschlikon, Switzerland IBM Systems and Technology, Rochester, MN 3 IBM Systems and Technology, Durham,
ISSCC 2021 Session 8 Wireline I/O
A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2
Marc-Andre LaCroix, Euhan Chong, Weilun Shen, Ehud Nir,
Faisal Ahmed Musa, Haitao Mei, Mohammad-Mahdi Mohsenpour, Semyon Lebedev, Babak Zamanlooy, Carlos Carvalho, Qian Xin, Dmitry Petrov, Henry Wong, Huong Ho, Yang Xu, Sina Naderi Shahi, Peter Krotnev, Chris Feist, Howard Hu
ISSCC 2021 Session 8 Wireline I/O
A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm
Danfeng Xu*1, Yu Kou*1, Paul Lai*,1, Zichuan Cheng1, Tze Yin Cheung2,
Larry Moser1, Yang Zhang1, Xiaolong Liu1, Man Pio Lam1, Haikun Jia2,3, Quan Pan2,4, Wing Hong Szeto2, Chi Fai Tang2, Ka Fai Mak2, Khawar Sarfraz2, Tairan Zhu1, Ming Kwan1, Emily Yim Lee Au1, Cormac Conroy1, Kai Keung Cha
ISSCC 2021 Session 8 Wireline I/O
A Highly Reconfigurable 40-97GS/s DAC and ADC with 40GHz AFE Bandwidth and Sub-35fJ/conv-step for 400Gb/s Coherent Optical Applications in 7nm FinFET
R. L. Nguyen1, A. M. Castrillon2, A. Fan1, A. Mellati1, B. T. Reyes2, C. Abidin1,
E. Olsen1, F. Ahmad1, G. Hatcher1, J. Chana3, L. Biolato2, L. Tse4, L. Wang1, L. Wang4, M. Azarmnia1, M. Davoodi1, N. Campos2, N. Fan1, P. Prabha1, Q. Lu1, S. Cyrusian1, S. Dallaire5, S. Ho3, S. Jantzi1, T. Dusatko3, W.
ISSCC 2021 Session 8 Wireline I/O
A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET peaking inductor is leveraged to resonate out the parasitic & transistor gate capacitances. A flipped voltage follower buffer is used to isolate the CTLE from the 16 TAHs. The DCgain normalized frequency response at the output of the AFE for various CTLE settings is shown in the Fig. 8.7.3.
P. Mishra1, A. Tan1, B. Helal1, C.R. Ho1, C. Loi1, J. Riani1, J. Sun2, K. Mistry3,
K. Raviprakash1, L. Tse1, M. Davoodi4, M. Takefman3, N. Fan4, P. Prabha4, Q. Liu2, Q. Wang1, R. Nagulapalli5, S. Cyrusian4, S. Jantzi4, S. Scouten3, T. Dusatko6, T. Setya3, V. Giridharan1, V. Gurumoorthy1, V. Karam3, W.
ISSCC 2021 Session 8 Wireline I/O
A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver
James Bailey1, Hossein Shakiba1, Ehud Nir2, Grigory Marderfeld2,
equalization (e.g. extensive FFE and DFE) of wireline channels. FFE and canonical DFE sizes scale linearly with the number of taps, however the computational complexity of an FFE is much greater than that of a DFE. The c
Peter Krotnev2, Marc-Andre LaCroix2, David Cassan1 Huawei Technologies
ISSCC 2021 Session 9 AI / ML
A 28nm 12.1TOPS/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based Prediction
Huiyu Mo1, Wenping Zhu1, Wenjing Hu1, Guangbin Wang1, Qiang Li2, Ang Li1,
edge devices efficiently, most existing CNN processors were built on quantized CNNs to optimize the inference operations. However, three issues (Fig. 9.2.1) have not been well addressed: 1) Duplicate weights in each kern
Shouyi Yin1, Shaojun Wei1, Leibo Liu1 Institute of Microelectronics of
ISSCC 2021 Session 9 AI / ML
A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree
Jeongwoo Park*, Sunwoo Lee*, Dongsuk Jeon
*Equally Credited Authors (ECAs) Recent works on mobile deep-learning processors have presented designs that exploit sparsity [2, 3], which is commonly found in various neural networks. However, due to the shift in the m
Seoul National University, Seoul, Korea
ISSCC 2021 Session 9 Digital Processors
PIU: A 248GOPS/W Stream-Based Processor for Irregular Probabilistic Inference Networks Using Precision-Scalable Posit Arithmetic in 28nm
Nimish Shah, Laura Isabel Galindez Olascoaga, Shirui Zhao, Wannes Meert, Marian Verhelst
devices, their usage is also criticized due to lack of explainability, inability to include domain knowledge, and a need for large volumes of training data. To overcome this, researchers are increasingly using probabilis
KU Leuven - MICAS, Leuven, Belgium While deep neural networks have bec
ISSCC 2021 Session 9 AI / ML
A 6K-MAC Feature-Map-Sparsity-Aware Neural Processing Unit in 5nm Flagship Mobile SoC
Jun-Seok Park1, Jun-Woo Jang2, Heonsoo Lee1, Dongwoo Lee1, Sehwan Lee2,
Hanwoong Jung2, Seungwon Lee2, Suknam Kwon1, Kyungah Jeong1, Joon-Ho Song2, SukHwan Lim1, Inyup Kang1 Samsung Electronics, Hwaseong, Korea Samsung Advanced Institute of Technology, Suwon, Korea 1 2 On-device machine lear
ISSCC 2021 Session 9 AI / ML
A 1/2.3inch 12.3Mpixel with On-Chip 4.97TOPS/W CNN Processor Back-Illuminated Stacked CMOS Image Sensor
Ryoji Eki1, Satoshi Yamada2, Hiroyuki Ozawa1, Hitoshi Kai1, Kazuyuki Okuike2,
Hareesh Gowtham2, Hidetomo Nakanishi2, Edan Almog3, Yoel Livne3, Gadi Yuval3, Eli Zyss3, Takashi Izawa2 Sony Semiconductor Solutions, Tokyo, Japan Sony Semiconductor Solutions, Atsugi, Japan 3 Sony Semiconductor Israel,
ISSCC 2021 Session 9 Digital Processors
A 184µW Real-Time Hand-Gesture Recognition System with Hybrid Tiny Classifiers for Smart Wearable Devices
Yuncheng Lu1, Van Loi Le2, Tony Tae-Hyoung Kim1
Nations Innovation Technologies, Singapore, Singapore 1 2 Recently, vision-based hand gesture recognition (HGR) has emerged as a natural and flexible human-computer interaction (HCI) approach. Users can control smart dev
Nanyang Technological University, Singapore, Singapore
ISSCC 2021 Session 9 Digital Processors
A 25mm2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET
Thierry Tambe1, En-Yu Yang1, Glenn G. Ko1, Yuji Chai1, Coleman Hooper1,
Marco Donato2, Paul N. Whatmough1,3, Alexander M. Rush4, David Brooks1, Gu-Yeon Wei1 Harvard University, Cambridge, MA Tufts University, Medford, MA 3 ARM, Boston, MA 4 Cornell University, New York, NY 1 2 Automatic spee
ISSCC 2021 Session 9 Digital Processors
A Background-Noise and Process-Variation-Tolerant 109nW Acoustic Feature Extractor Based on Spike-Domain DivisiveEnergy Normalization for an Always-On Keyword Spotting Device
Dewei Wang, Sung Justin Kim, Minhao Yang, Aurel A. Lazar, Mingoo Seok
In mobile and edge devices, always-on keyword spotting (KWS) is an essential function to detect wake-up words. Recent works achieved extremely low power dissipation down to ~500nW [1]. However, most of them adopt noise-d
Columbia University, New York, NY