ISSCC 2022
Session 24
RF & Wireless
A 22nm 0.84mm2 BLE Transceiver with Self IQ-Phase Correction Achieving 39dB Image Rejection and On-Chip Antenna Impedance Tuning
Figure 24.4.4 shows the proposed AIT providing optimum impedance matching for RX Kenichi Shibata, Hiroaki Matsui, Hironori Asano, Yuichi Kusaka, Keisuke Ueda, and TX independently with a wide impedance tunability. In TX
ISSCC 2022
Session 24
RF & Wireless
A 266µW Bluetooth Low-Energy (BLE) Receiver Featuring an N-Path Passive Balun-LNA and a Pipeline Down-Mixing BB-Extraction Scheme Achieving 77dB SFDR and -3dBm OOB-B-1dB
University of Lisboa, Lisbon, Portugal 1 3 Ultra-low-power short-range radios are the cornerstone of building a world with the Internet-of-Everything connectivity. To secure a high sensitivity at a sub-mW power budget, s
ISSCC 2022
Session 24
RF & Wireless
A 110µW 2.5kb/s -103dBm-Sensitivity Dual-Chirp Modulated ULP Receiver Achieving -41dB SIR
*Equally-Credited Authors (ECAs) As the number of devices connected to the IoT has increased rapidly in recent years, stricter requirements have been placed on IoT radio receivers (RX) that can operate in an increasingly
ISSCC 2022
Session 24
RF & Wireless
An LPWAN Radio with a Reconfigurable Data/Duty-CycledWake-Up Receiver
Demands for the low-power wide-area network (LPWAN) are increasing along with a growing market for low data-rate, long-range internet of things (IoT) applications. Although many radios have been released for various LPWA
ISSCC 2022
Session 25
Data Converters
A 4.4µW 2.5kHz-BW 92.1dB-SNDR 3rd-Order VCO-Based ADC with Pseudo Virtual Ground Feedforward Linearization
The rise of the internet-of-things and distributed sensor nodes with machine-learning and edge processing are driving the need for low-power, high-precision ADCs. These highly digital systems are best implemented in adva
ISSCC 2022
Session 25
Data Converters
A 2.87µW 1kHz-BW 94.0dB-SNDR 2-0 MASH ADC using FIA with Dynamic-Body-Biasing Assisted CLS Technique
Peking University, Beijing, China 1 2 Micro-power ∆Σ modulators are suitable for low-bandwidth, high-precision applications, such as smart sensors, biomedical signal processing and battery-powered IoT devices. They achie
ISSCC 2022
Session 25
Data Converters
A 0.0375mm2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS
Demands for battery-powered consumer electronics have driven the evolution of powerefficient high-resolution low-bandwidth ADCs. Small area and low power are both critical for these applications due to increasing battery
ISSCC 2022
Session 25
Data Converters
A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ∆Σ ADC in 40nm CMOS
University of Technology, Delft, The Netherlands 1 2 In the pursuit of ever larger bandwidths, in recent years GHz-rate continuous-time (CT) oversampled ADCs have been reported in literature that achieve bandwidths of hu
ISSCC 2022
Session 25
Data Converters
A 28nm 6GHz 2b Continuous-Time ∆Σ ADC with -101dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction
continuous-time ∆Σ modulators with a (theoretically) linear 1b DAC, have demonstrated better than -100dBc THD in a bandwidth range from tens of kHz for audio to tens of MHz for broadband AM/FM radio [1]. To achieve both
ISSCC 2022
Session 25
Data Converters
An 84dB-SNDR Low-OSR 4th-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique
*Equally Credited Authors (ECAs) With the combined merits of SAR and ∆Σ ADCs, the noise-shaping (NS) SAR architecture can achieve high resolution with a mild OSR, making it versatile for a wide range of applications. Non
ISSCC 2022
Session 26
Quantum & Photonics
Beyond-Classical Computing Using Superconducting Quantum Processors Joseph Bardin
quantum computer. Of the technologies available to implement the quantum processor at the core of such a system, solid-state superconducting circuits based on Josephson junctions (JJs) are among the strongest contenders.
ISSCC 2022
Session 26
Quantum & Photonics
Design Considerations for Superconducting Quantum Systems
J. Watson Research Center, Yorktown Heights, NY 1 2 *Equally Credited Authors (ECAs) A distinguishing feature of quantum system engineering is that it must contend with the nature of “quantum processors” as extended obje
ISSCC 2022
Session 26
Quantum & Photonics
Augmented Reality – The Next Frontier of Image Sensors and Compute Systems
Augmented Reality (AR) will be the next great wave of human-oriented computing, dominating our relationship with the digital world for the next 50 years, much as personal computing has dominated the last 50 [1]. AR glass
ISSCC 2022
Session 26
Quantum & Photonics
3D V-Cache: The Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU
3D stacked product that attaches additional cache onto a high-performance processor through hybrid bonding, a technology that offers significant bandwidth and power benefits over state-of-the-art uBump based approaches.
ISSCC 2022
Session 27
mm-Wave
A Power-Efficient 24-to-71GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36dB Inter-Band Blocker Rejection for 5G NR
Multi-band receivers have been developed to realize reception over multiple 5G FR2 bands with minimized system size [1-3]. The conventional multi-band receiver achieves 20-to-44GHz frequency coverage with wide-band RF re
ISSCC 2022
Session 27
mm-Wave
A 24-to-30GHz 256-Element Dual-Polarized 5G Phased Array
Bodhisatwa Sadhu1, Arun Paidimarri1, Wooram Lee1, Mark Yeck1, Caglar Ozdag1, Yujiro Tojo2, Jean-Olivier Plouchart1, Xiaoxiong Gu1, Yusuke Uemichi2, Sudipto Chakraborty1, Yo Yamaguchi2, Ning Guan2, Alberto Valdes-Garcia1
ISSCC 2022
Session 27
mm-Wave
A Hybrid Coupler-First 5GHz Noise-Cancelling Dual-Mode Receiver with +10dBm In-Band IIP3 in Current-Mode and 1.7dB NF in Voltage-Mode
out-of-band(OOB) linearity for sub-6GHz applications [1-3]. To achieve high linearity, one solution is to utilize current-mode direct conversion [1]. In this architecture, the low-noise amplifier (LNA) acts as a transcon
ISSCC 2022
Session 27
mm-Wave
A Single-Path Digital-IF Receiver Supporting Inter/Intra 5-CA with a Single Integer LO-PLL in 14nm CMOS FinFET
Ilhoon Jang, Youngmin Kim, Anna Yu, Jong-Hyun Jang, Jiyoung Lee, Jeongyeol Bae, Euiyoung Park, Sungjun Lee, Seokwon Lee, Joohan Kim, Beomkon Kim, Yong Lim, Seunghyun Oh, Jongwoo Lee, Byunghak Cho, Inyup Kang Samsung Elec
ISSCC 2022
Session 28
Memory
A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV AutoCalibration Scheme and Machine-Learning-Based Layout Optimization
Sangsic Yoon, Dong Uk Lee, Seokwoo Choi, Jihwan Park, Jinhyung Lee, Kyungjun Cho, Junil Moon, Byung-Kuk Yoon, Young-Jun Park, Sang-muk Oh, Chang Kwon Lee, Tae-Kyun Kim, Seong-Hee Lee, Hyun-Woo Kim, Yucheon Ju, Seung-Kyun
ISSCC 2022
Session 28
Memory
A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with
frequency. When LF_ON is low (LF_ONB is high), the CML resistance and its current changes in the opposite direction and the center frequency is close to 12GHz (24Gb/s). As a result, the proposed frequency divider covers
ISSCC 2022
Session 28
Memory
A 16Gb 9.5Gb/s/pin LPDDR5X SDRAM with Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process
Seokjin Cho, Kihan Kim, Seung-Hoon Oh, Hye-Yoon Joo, Geuntae Park, Jin-Hun Jang, Yong-Hun Kim, Donghun Lee, Jaehoon Jung, Yongmin Kwon, Youngjae Kim, Jaewoo Jung, Seongil O, Seoulmin Lee, Jaeseong Lim, Junho Son, Jisu Mi
ISSCC 2022
Session 28
Memory
A 20 Gb/s/pin 1.18pJ/b 1149µm2 Single-Ended Inverter-based 4-tap Addition-Only Feed-Forward Equalization Transmitter with Improved Robustness to Coefficient Errors in 28nm CMOS
matching method [3], the signal integrity problems are resolved by matching the farend terminal to 50Ω. This technique can improve the voltage swing of the inverters. The half-rate digital inputs are serialized by the re
ISSCC 2022
Session 28
Memory
A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver
Hyunsu Park1, Yoonjae Choi1, Jincheol Sim1, Jonghyuck Choi1, Youngwook Kwon1, Junyoung Song2, Chulwoo Kim1 Korea University, Seoul, Korea Incheon National University, Incheon, Korea 1 2 The bandwidth of parallel DRAM I/O
ISSCC 2022
Session 28
Memory
A 78.8fJ/b/mm 12.0Gb/s/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOS
Advances in virtual reality, artificial intelligence, and big data have increased demand for high-bandwidth memory. Accordingly, pre-fetch sizes have also increased with DRAM generations, meaning an increased number of g
ISSCC 2022
Session 28
Memory
A 20-Gb/s/pin 0.0024-mm2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces
Samsung Electronics, Hwaseong, Korea SSC DECS input, the resulting clock and data paths are equally matched and the impact of the RX SN on the RX performance is minimized. In a conventional RX the sampling clock is gener
ISSCC 2022
Session 28
Memory
A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter
SK hynix, Icheon, Korea 3 Korea Aerospace Research Institute, Daejeon, Korea 4 KAIST, Daejeon, Korea 1 2 *Equally Credited Authors (ECAs) With the increasing demand for low-power, high-speed DRAMs, LPDDR5 featuring a spe
ISSCC 2022
Session 29
Other
184QPS/W 64Mb/mm2 3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System
Tianchan Guan3, Fei Sun1, Fei Xue1, Lide Duan1, Yuanwei Fang1, Hongzhong Zheng1, Xiping Jiang4, Song Wang4, Fengguo Zuo4, Yubing Wang4, Bing Yu4, Qiwei Ren4, Yuan Xie1 Alibaba DAMO Academy, Sunnyvale, CA; 2Alibaba DAMO A
ISSCC 2022
Session 29
AI / ML
A 28nm 27.5TOPS/W Approximate-Computing-Based Transformer Processor with Asymptotic Sparsity Speculating and Out-of-Order Computing
code generator performs cascaded OR (AND) for positive (negative) data via 6b MSBs to generate a 6b signal with more 0-bits for small values to disable compressors. For exact mode, it modifies 2 BVs to “0” to make approx
ISSCC 2022
Session 29
AI / ML
A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes
state-of-the-art results in many fields, like natural language processing and computer vision, but their large number of matrix multiplications (MM) result in substantial data movement and computation, causing high laten
ISSCC 2022
Session 29
AI / ML
ReckOn: A 28nm Sub-mm2 Task-Agnostic Spiking Recurrent Neural Network Processor Enabling On-Chip Learning over Second-Long Timescales
The robustness of autonomous inference-only devices deployed in the real world is limited by data distribution changes induced by different users, environments, and task requirements. This challenge calls for the develop
ISSCC 2022
Session 30
Power Management
A 32nA Fully Autonomous Multi-Input Single-Inductor Multi-Output Energy-Harvesting and Power-Management
Shuo Li, Xinjian Liu, Benton H. Calhoun University of Virginia, Charlottesville, VA Energy harvesting and power management units (EHPMUs) are gaining popularity for self-powered Internet-of-Things (IoT) applications due
ISSCC 2022
Session 30
Power Management
A 130V Triboelectric Energy-Harvesting Interface in 0.18µm BCD with Scalable Multi-Chip-Stacked Bias-Flip and Daisy-Chained Synchronous Signaling Technique
vibration energy have gained popularity as a next-generation energy source owing to their numerous advantages including flexibility, high conversion efficiency, and low cost. However, ultrahigh instantaneous open-circuit
ISSCC 2022
Session 30
Power Management
A Reconfigurable Series-Parallel Charger for Dual-Battery Applications with 89W 97.7% Efficiency in Direct Charging Mode
foldable phones, the number of smart phones that use two batteries are gradually increasing [1]. In ultra-fast charging applications, two batteries are connected in series as shown in Fig. 30.3.1. The output voltage of t
ISSCC 2022
Session 30
Power Management
A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer
compute/memory and analog/mixed-signal circuits such as SerDes transceivers, RF/wireless front-end, PLLs, sensors, etc. On-chip low-dropout regulators (LDOs) isolate the input Vin noise from switching DC-DC converters po
ISSCC 2022
Session 31
Other
A -117dBc THD (-132dBc HD3) and 126dB DR Audio Decoder with Code-Change-Insensitive RT-DEM Algorithm and Circuit Technique for Relaxing Velocity Saturation Effect of Poly Resistors
inter-symbol interference (ISI) [1,2]; 2) 3rd-order harmonic distortion (HD3) due to the 2nd-order nonlinearity of poly resistors; and 3) Cross-over distortion (COD) arising from limited amplifier inner-loop gain due to
ISSCC 2022
Session 31
Other
A 121dB DR, 0.0017% THD+N, 8× Jitter-Effect Reduction Digital-Input Class-D Audio Amplifier with Supply-VoltageScaling Volume Control and Series-Connected DSM
Class-D audio amplifiers have gradually become standard components in mobile devices, where better audio quality over a wide volume range and higher output power (POUT) are desired. However, in mobile devices, the POUT i
ISSCC 2022
Session 31
Other
A -91dB THD+N Resistor-Less Class-D Piezoelectric Speaker Driver Using a Dual Voltage/ Current Feedback for LC Resonance Damping
Goodix Technology, Nijmegen, The Netherlands 1 2 Piezoelectric speakers are gaining popularity on account of their improving form-factor and audio quality, making them a good fit for many audio applications such as in te
ISSCC 2022
Session 32
Other
BatDrone: A 9.83M-focal-points/s 7.76µs-Latency Ultrasound Imaging System with On-Chip Per-Voxel RX Beamfocusing for 7m-Range Drone Applications
Yilong#Dong1, Miaolin#Zhang1, Zhuoyue#Li1, Kian#Ann#Ng3, Chne-Wuen#Tsai1, Lian#Zhang1, Longyang#Lin4, Liwei#Lin2, Jerald#Yoo1,5 National University of Singapore, Singapore, Singapore University of California, Berkeley, C
ISSCC 2022
Session 32
Other
A Pitch-Matched ASIC with Integrated 65V TX and Shared Hybrid Beamforming ADC for Catheter-Based High-FrameRate 3D Ultrasound Probes
Zu-Yao Chang1, Chao Chen1, Hendrik Vos1,2, Hans Bosch2, Martin Verweij1,2, Nico de Jong1,2, Michiel Pertijs1 Delft University of Technology, Delft, The Netherlands Erasmus MC, Rotterdam, The Netherlands 1 2 Intra-cardiac
ISSCC 2022
Session 32
Other
A 1.2mW/channel 100µm-Pitch-Matched Transceiver ASIC with Boxcar-Integration-Based RX Micro-Beamformer for High-Resolution 3D Ultrasound Imaging
Johan G. Bosch2, Martin D. Verweij1,2, Nico de Jong1,2, Michiel A. P. Pertijs1 Delft University of Technology, Delft, The Netherlands 2 Erasmus MC, Rotterdam, The Netherlands 1 The integration of 2D ultrasonic transducer
ISSCC 2022
Session 32
Other
An Electronically Tunable Multi-Frequency Air-Coupled CMUT Receiver Array with sub-100µPa Minimum Detectable Pressure Achieving a 28kb/s Wireless Uplink Across a Water-Air Interface
Oceans play a critical role in our ecosystem – they regulate weather and global temperature, serve as the largest carbon sink and the greatest source of oxygen. Maintaining ocean health is of paramount importance and has
ISSCC 2022
Session 32
Other
A Multimode 157µW 4-Channel 80dBA-SNDR Speech-Recognition Frontend with Self-DOA Correction Adaptive Beamformer
Mohammad R. Haghighat2, Michael P. Flynn1 *Equally-Credited Authors (ECAs) 1 University of Michigan, Ann Arbor, MI; 2Intel, Santa Clara, CA Beamforming with multiple microphones is essential for Automatic Speech Recognit
ISSCC 2022
Session 33
Digital Processors
A 1.05A/m Minimum Magnetic Field Strength Single-Chip Fully Integrated Biometric Smart Card SoC Achieving 1014.7ms Transaction Time with Anti-Spoofing Fingerprint Authentication
Gi-Jin Kang, Junho Kim, Shin-Wuk Kang, Uijong Song, Chang-Yeon Cho, Junseo Lee, Kyungduck Seo, Seongwook Song, Sung Ung Kwak Samsung Electronics, Hwaseong, Korea Biometric authentication is a proven and practical way to
ISSCC 2022
Session 33
Digital Processors
A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction
Epilepsy is a common neurodegenerative disease that affects more than 50 million people worldwide. Closed-loop neuromodulation is a promising solution to epileptic seizure control through an implantable device that deliv
ISSCC 2022
Session 33
Digital Processors
A HD 31fps 7×7-View Light-Field Factorization Processor for Dual-Layer 3D Factored Display
provides a fullparallax glasses-free 3D viewing experience. Compared to other autostereoscopic techniques, factored displays provide greater depth of field, larger field of view, and smoother perspective switching withou
ISSCC 2022
Session 33
AI / ML
DSPU: A 281.6mW Real-Time Depth Signal Processing Unit for Deep Learning-Based Dense RGB-D Data Acquisition with Depth Fusion and 3D Bounding Box Extraction in Mobile Platforms
RGBD data and 3D bounding-box (BB) information for accurate navigation and seamless interaction with the surrounding environment. Specifically, the extraction of RGB-D data and 3D BB needs to be done in real-time (> 30fp
ISSCC 2022
Session 34
Hardware Security
A 28nm 48KOPS 3.4µJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems
era, post-quantum cryptography (PQC) processors are required to ensure quantum-secure communication and e-commerce with high throughput, while maintaining adequate flexibility to execute different crypto-primitives, such
ISSCC 2022
Session 34
AI / ML
Side-Channel Attack Counteraction via Machine LearningTargeted Power Compensation for Post-Silicon HW Security Patching
Southern University of Science and Technology, Shenzhen, China 1 2 *Equally Credited Authors (ECAs) Counteracting side-channel attacks has become a basic requirement in secure integrated circuits handling physical or sen
ISSCC 2022
Session 34
Hardware Security
A Threshold-Implementation-Based Neural-Network Accelerator Securing Model Parameters and Inputs Against Power Side-Channel Attacks
Indian Institute of Science, Bengaluru, India 3 Analog Devices, Wilmington, MA 1 2 Neural network (NN) hardware accelerators are being widely deployed on low-power IoT nodes for energy-efficient decision making. Embedded
ISSCC 2022
Session 34
Hardware Security
An 8.3-to-18Gbps Reconfigurable SCA-Resistant/DualCore/Blind-Bulk AES Engine in Intel 4 CMOS
Amit Agarwal, Vivek K. De, Sanu K. Mathew Intel, Hillsboro, OR Power and electromagnetic (EM) side-channel attacks (SCA) exploit data-dependent power consumption from cryptographic engines to extract embedded secret keys