ISSCC 2025

2025

242 篇论文 · Power Management (28) · AI / ML (24) · RF & Wireless (23) · Medical & Bio (19)

ISSCC 2025 Session 23 Other
Nebula: A 28nm 109.8TOPS/W 3D PNN Accelerator Featuring
Adaptive Partition, Multi-Skipping, and Block-Wise Aggregation
Changchun Zhou1, Tianling Huang1, Yanzhe Ma1, Yuzhe Fu1, Xiangjie Song1, Siyuan Qiu1, Jiacong Sun1, Min Liu1, Ge Li1, Yifan He2, Yuchao Yang1,3, Hailong Jiao1 Peking University, Shenzhen, China Reconova Technologies, Xia
ISSCC 2025 Session 23 Other
MAE: A 3nm 0.168mm2 576MAC Mini AutoEncoder with Line-based Depth-First Scheduling for Generative AI in Vision on Edge Devices
Shih-Wei Hsieh, Chia-Hung Yuan, Ming-Hung Lin, Ping-Yuan Tsai, You-Yu Nian,
Chia-Yuan Cheng, Hung-Wei Chih, Po-Han Chiang, Ming-Hsuan Chiang, Yuan-Jung Kuo, Yu-Wei Wu, Yi-Syuan Chen, Po-Heng Chen, Sandy Huang, Ming-En Shih, Chia-Ping Chen, Abrams Chen, ShenKai Chang, Chih-Ming Wang, Po-Yu Yeh, J
ISSCC 2025 Session 23 Other
MEGA.mini: A Universal Generative AI Processor with a New Big/Little Core Architecture for NPU
Donghyeon Han1,2, Anantha P. Chandrakasan1
Chung-Ang University, Seoul, Korea 1 2 The global AI market is growing explosively with the rise of generative AI applications, such as image manipulation and text-to-text/image/video creation. AI was primarily expected
Massachusetts Institute of Technology, Cambridge, MA
ISSCC 2025 Session 23 Other
BROCA: A 52.4-to-559.2mW Mobile Social Agent System-on-Chip with Adaptive Bit-Truncate Unit and Acoustic-Cluster Bit Grouping computation. The ACE PE processes input data in a bit-serial manner, where four 8b weights are accumulated in parallel, leading to a decrease in compute energy proportional to the input bitwidth. As a result, an average reduction of 4.4b in input bitwidth and a 4.7× speedup can be achieved, reducing computation energy by 44.5% at the RG.
Wooyoung Jo, Seongyon Hong, Jiwon Choi, Beomseok Kwon, Haoyang Sang,
Dongseok Im, Sangyeob Kim, Sangjin Kim, Taekwon Lee, Hoi-Jun Yoo Figure 23.7.4 illustrates the proposed ACBU, which achieves runtime bitwidth reduction of the vocoder input feature map to reduce computation energy in the
ISSCC 2025 Session 23 Other
An 88.36TOPS/W Bit-Level-Weight-Compressed Large-Language-Model Accelerator with Cluster-Aligned INT-FP-GEMM and Bi-Dimensional Workflow Reformulation
Yubin Qin, Yang Wang, Jiachen Wang, Zhiwei Lin, Yushu Zhao, Shaojun Wei,
range of natural language processing (NLP) tasks, becoming an essential part of modern society [1-4]. This exceptional performance can be attributed to huge model size and autoregressive computation [5,6]. However, these
Yang Hu, Shouyi Yin Tsinghua University, Beijing, China Large language
ISSCC 2025 Session 23 Other
Slim-Llama: A 4.69mW Large-Language-Model Processor with Binary/Ternary Weights for Billion-Parameter Llama Model
Sangyeob Kim, Jungwan Lee, Hoi-Jun Yoo
Recently, multiple ASICs [1-6] have been proposed to accelerate large language models (LLMs). However, the enormous number of LLM parameters leads to significant energy consumption due to external memory access (EMA). Wh
KAIST, Daejeon, Korea
ISSCC 2025 Session 24 Data Converters
A 12b 3GS/s Pipelined ADC with Gated-LMS-Based Piecewise-Linear Nonlinearity Calibration
Mingyang Gu, Yi Zhong, Lu Jie, Nan Sun
The pipelined ADC is an attractive choice for high-speed and high-resolution applications. Its most important building block is the residue amplifier. Compared with conventional closed-loop amplifiers, open-loop amplifie
Tsinghua University, Beijing, China
ISSCC 2025 Session 24 Data Converters
A 14b 1GS/s Single-Channel Pipelined ADC with a Parallel-Operation SAR Sub-Quantizer and a DynamicDeadzone Ring Amplifier
Yue Cao1, Yi Shen1,2, Shubin Liu1,2, Haolin Han1, Hongzhi Liang1, Li Dang1,
and high resolution (&14b) are required for wireless communication and instrumentation applications. The conventional pipelined architecture is usually power-hungry due to the substantial use of residue amplifiers (RAs)
Dengquan Li1, Ruixue Ding1,2, Zhangming Zhu1,2 Xidian University, Xi’a
ISSCC 2025 Session 24 Data Converters
A PVT-Robust 2× Interleaved 2.2GS/s ADC with Gated-CCRO-Based Quantizer Shared Across Channels and Steps Achieving >4.5GHz ERBW
Junlin Zhong1, Minglei Zhang1, Yan Zhu1, Rui P. Martins1,2, Chi-Hang Chan1
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 The demand for medium-resolution GS/s ADCs is increasing in DSP-based wireline communication. Enhancing energy and area efficiency of the unit ADC is cr
University of Macau, Macau, China
ISSCC 2025 Session 24 Data Converters
A 10b 3GS/s Time-Domain ADC with Mutually Exclusive Metastability Correction and Wide Common-Mode Input
Zijian Liu1, Minglei Zhang1, Wei Zhang1, Yan Zhu1, Rui P. Martins1,2, Chi-Hang Chan1
unpredictable and non-Gaussian error behaviors in the A/D conversion, which cannot be tolerated by applications such as lowbit-error-rate serial link receivers, radar, and instrumentation [1-5]. Time-domain (TD) ADCs [6-
University of Macau, Macau, China Instituto Superior Tecnico/Universit
ISSCC 2025 Session 24 Data Converters
A 72GS/s 9b Time-Interleaved Pipeline-SAR ADC Achieving 55.3/49.3dB SFDR at 20GHz/Nyquist Inputs in 16nm FinFET
Yannan Zhang1, Minglei Zhang1, Zehang Wu1, Yan Zhu1, Rui P. Martins1,2, Chi-Hang Chan1
traffic have driven optical modules to scale beyond 100Gb/s. This evolves aggressive bandwidth and SNDR frontiers for their ADCs in the receiver to cope with advanced modulations and oversampling rates. Time-interleaving
University of Macau, Macau, China Instituto Superior Tecnico/Universit
ISSCC 2025 Session 24 Data Converters
A Power- and Area-Efficient 4nm Self-Calibrated 12b/16GS/s Hierarchical Time-Interleaving ADC
Cheng-En Hsieh*1, Gabriele Manganaro*2, Sheng-Hui Liao*1, Jack Weng*1,
Tsun-Yuan Fan1, Alec Chin1, Tsung-Chih Hung1, Jonathan X Wu2, Chi-Lun Lo2, Andy Pan1, Ming-Hang Hsieh1, Yun-Shiang Shu1, Wei-Hsin Tseng1, Kuan-Dar Chen1 MediaTek, Hsinchu, Taiwan MediaTek, Woburn, MA 1 Each sub-ADC, cloc
ISSCC 2025 Session 24 Data Converters
An 8b 10GS/s 2-Channel Time-Interleaved Pipelined ADC with
Concurrent Residue Transfer and Quantization, and Automatic, Buffer Power Gating
Yunsong Tao, Mingtao Zhan, Mingyang Gu, Xiyu He, Yuxuan He, Zhishuai Zhang, Yi Zhong, Lu Jie, Nan Sun Tsinghua University, Beijing, China High-speed (~10GS/s) medium-resolution (~8b) ADCs are key blocks for wideband appl
ISSCC 2025 Session 24 Data Converters
A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET
Junhua Shen1, Wei-Hung Chen2, Efram Burlingame3, Stephen Weinreich1,
Michael Elliott4, Stuart McCracken1, Jack Kenney2, Janet Brunsilius3, Anil Korkmaz5, Enrique Alvarez Fontecilla3, Nevena Rakuljic3, Ushma Mehta3, Ben Sullivan1, Jeremy Scuteri5, Bac Binh Luu3, Mitchell Nichols3, Dara Mar
ISSCC 2025 Session 25 Other
A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100% Solvability and 31.7μs Solution Time
Evangelos Dikopoulos, Ying-Tuan Hsu*, Luke Wormald*, Wei Tang,
Zhengya Zhang, Michael P. Flynn University of Michigan, Ann Arbor, MI *Equally Credited Authors (ECAs) The Boolean satisfiability (SAT) problem is a fundamental NP-complete problem, and efficiently solving it would revol
ISSCC 2025 Session 25 Other
A 4GS/s Fully Analog 256×256 MP-Based Cross-Correlator with 1000TOPS/W Compute Efficiency and 1.3TOPS/mm2 Compute Density in 22nm SOI CMOS
Aswin Undavalli1, Kareem Rashed2, Gert Cauwenberghs3, Shantanu Chakrabartty1,
Louis, Saint Louis, MO Oregon State University, Corvallis, OR 3 University of California, San Diego, CA 4 Northeastern University, Oakland, CA 1 2 Multi-lag cross-correlations (X-Corr) are essential building blocks in ra
Arun Natarajan2, Aravind Nagulu1,4 Washington University in St
ISSCC 2025 Session 25 Other
AI-Enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mm-Wave/sub-THz PAs between 30 and 120GHz
Jonathan Zhou*1, Emir Ali Karahan*1, Sherif Ghozzy1, Zheng Liu1,2, Hossein Jalili1, Kaushik Sengupta1
AI-enabled algorithmic flow for architecture discovery, circuit topology and parameter optimization for RFICs, particularly exploring design spaces beyond human intuition. RF and mmWave IC design is a complex iterative d
Princeton University, Princeton, NJ Texas Instruments, Dallas, TX 1 2
ISSCC 2025 Session 25 Other
A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz
Jesse Moody, Tyler Liebsch, Patrick Finnegan, Stefan Lepkowski,
integrated microsystems becomes increasingly difficult as these systems scale in size and speed. These interfaces are tight pitch and parasitic sensitive, limiting the use of traditional (50Ω) test equipment. A microscal
Robert Costanzo, Mieko Hirabayashi, Matt Jordan, Travis Forbes, Christ
ISSCC 2025 Session 25 Other
A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS
Guangdong Wu*1, Yuanliang Li*1, Bingyi Ye*1,2, Fangzhu Li1, Xin Liu1, Haowei Niu1,
Beijing, China 1 2 *Equally Credited Authors (ECAs) The growing demand for higher network bandwidth has led to a significant rise in channel density within Ethernet switches and high-performance computers. As data rates
Ruixu Wang1, Dunshan Yu1, Weixin Gai1,3 Peking University, Beijing, Ch
ISSCC 2025 Session 26 Wireless
A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and -30.8dB EVM in 65nm CMOS
Soumya Mahapatra1, Mostafa Ayesh1, Ce Yang1, Mayank Palaria1, Shiyu Su1,2,
employment of K/Ka-band for sensing and communication purposes, such as 5G systems and radar applications, has gained increasing interest. These systems commonly make use of an array of transmitters (TX) and antennas, ea
Aoyang Zhang3, Mike Shuo-Wei Chen1 University of Southern California,
ISSCC 2025 Session 26 Wireless
A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOS
Chunxiao Hu*, Jiaxiang Li*, Jie Lin, Hongtao Xu, Yun Yin
*Equally Credited Authors (ECAs) There are multiple wireless communication standards in the crowded sub-6GHz band and the trend of data throughputs is continuously increasing. In the last few years, digital transmitters
Fudan University, Shanghai, China
ISSCC 2025 Session 26 Wireless
A Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity
Yi Shen, Boxuan Chang, Chien-Wei Tseng, Yunfan Wang, Qirui Zhang,
wireless communication solutions remain critical for applications like smart-home automation and wearable health monitors. While IoT gateways can provide high-performance RF transceivers and powerful digital processors f
Zichen Fan, Zhen Feng, Rahul Narashimha, Andrea Bejarano-Carbo, Hun-Se
ISSCC 2025 Session 26 Wireless
A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2 Area
Xiaohan Zhang*, Ruizhe Wang*, Qiang Zhou*, Hao Guo, Chuan Shi, Taiyun Chi
*Equally Credited Authors (ECAs) The performance of mm-wave beamformers is largely determined by the front-end module (FEM), which integrates a power amplifier (PA), a low-noise amplifier (LNA), and a transmit/receive (T
Rice University, Houston, TX
ISSCC 2025 Session 26 Wireless
A 17.7-to-29.5GHz Transceiver Front-End with 3.3dB NF and 20.2dBm OP1dB in 65nm CMOS
Botao Yang1, Nayu Li2, Yiwei Liu1, Hang Lu1, Huiyan Gao1, Shaogang Wang1,
Shanghai, China 4 Georgia Institute of Technology, Atlanta, GA 1 2 To support various emerging applications, such as 5G millimeter-wave (mm-wave) communications, low-earth-orbit (LEO) satellite communication (SATCOM), an
Jingwen Xu1, Xuanyu He1, Na Yan3, Qun Jane Gu4, Chunyi Song2, Zhiwei X
ISSCC 2025 Session 27 RF & Wireless
A 3-Axis MEMS Gyroscope with 2.8ms Wake-Up Time Enabled by a 1.5µW Always-On Drive Loop
Longjie Zhong1, Jinwen Zhang1, Chengyue Li1, Ling Wang1, Mingsheng Zhong1,
mobile and wearable devices with human-machine interfaces for motion detection and indoor navigation [1-5]. In these applications, the always-on mode (i.e., standby or suspend mode) is required to support event-driven op
Kangkang Cai2, Ji Gao2, Tiegang Hu2, Zhangming Zhu1 Xidian University,
ISSCC 2025 Session 27 RF & Wireless
A Voltage-Biased CMOS Hall Sensor with 1.0µT (3σ) Offset and a 60nT/√Hz Noise-Floor
Floris J. P. van Mourik1, Sining Pan2, Karen M. Dowling1, Kofi A. A. Makinwa1
Tsinghua University, Beijing, China 1 2 Hall sensors are the only CMOS devices capable of measuring DC magnetic fields and so they are used in a wide range of applications, such as in compasses and current sensors. In su
TU Delft, Delft, The Netherlands
ISSCC 2025 Session 27 RF & Wireless
A Sub-1V 14b 5.8nW/Hz BW/Power-Scalable CT Sensor Interface with a Frequency-Controlled Current Source Achieving a 225× Scalable Range
Xinjie Wu1, Yuyan Liu2, Xiaopeng Yu1, Nick Nianxiong Tan2, Zhong Tang2
Vango Technologies, Hangzhou, China 1 2 Precision and energy-efficient sensor interfaces have always been needed in IoT applications. To digitize weak signals (tens of mVs), such as shunt-based current and biomedical sen
Zhejiang University, Hangzhou, China
ISSCC 2025 Session 27 RF & Wireless
A BJT-Based Temperature Sensor with an 80fJ∙K2 Resolution FoM
Nandor G. Toth, Kofi A. A. Makinwa
BJT-based temperature sensors are widely used because they can achieve a high accuracy after applying a low-cost 1-point trim. In terms of energy efficiency, however, they are still outperformed by resistor-based sensors
TU Delft, Delft, The Netherlands
ISSCC 2025 Session 28 Sensors
An 18.5nF-Input-Range PM-SAR-Hybrid Capacitance-to-Digital Converter Achieving 6.1µs Conversion Time at 18.1pF Input Capacitance
Donghyun Youn1, Kyeongwon Jeong2, Woongro Youn1, Hoyong Seong1,
S-OSC and R-OSC (S-DIV and R-DIV) derive a time difference ∆TSU+N·∆T, which is then converted to ∆VSU+∆V and D2[k] in the same manner. Finally, the kth C2D conversion result DLSB[k] is obtained as D1[k]%D2[k], so it cont
Yechan Park1, Sohmyung Ha3, Minkyu Je1 KAIST, Daejeon, Korea ETH Züric
ISSCC 2025 Session 28 Sensors
A 189.3dB-FoMS 14.5fJ/Conversion-Step Continuous-Time Noise-Shaping SAR Capacitance-to-Digital Converter
Gichan Yun1, Haidam Choi1, Yoontae Jung1,2, Jiho Myung1, Sein Oh1,
capacitance-to-digital converters (CDCs) have attracted significant attention in IoT applications to monitor environmental conditions such as humidity [1-3] and pressure [3-5]. One of the key challenges is how accurately
Sohmyung Ha3, Minkyu Je1 KAIST, Daejeon, Korea, *now at imec, Leuven,
ISSCC 2025 Session 28 Sensors
A 185.2dB-FoMs 8.7aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique
Bingrui Li, Zilong Shen, Haoyang Luo, Jiachang Yang, Zongnan Wang,
traditional lowspeed fields, such as measuring pressure [1] and humidity [2], to real-time applications like robotics and drones. E.g., high-performance MEMS motion-tracking devices feature a short measurement time of 31
Yuan Wang, Xiyuan Tang Peking University, Beijing, China Recent advanc
ISSCC 2025 Session 28 Sensors
A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing
Sining Pan1, Xiaolong Zhang1, Baoyi Zheng1, Yihang Cheng1, Hui Jiang2, Huaqiang Wu1
systems [1-4]. Compared to eddy-current displacement sensors [1], capacitive displacement sensors are potentially more energy efficient [2-4]. However, they are more susceptible to electric-field interferences on an elec
Tsinghua University, Beijing, China CoSensing, Utrecht, The Netherland
ISSCC 2025 Session 29 Memory
A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute
Tsung-Yung Jonathan Chang, Yen-Huei Chen, K. Venkateswara Reddy, Nikhil Puri,
Teja Masina, Kuo-Cheng Lin, Po-Sheng Wang, Yangsyu Lin, Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, Ku-Feng Lin, Ming-Hung Chang, Ching Wei Wu, Robin Lee, Yih Wang, Hung-Jen Liao, Quincy Li, Ping Wei Wang, Geoffrey Yea
ISSCC 2025 Session 29 Memory
A 0.021μm2 High-Density SRAM in Intel-18A-RibbonFET Technology with PowerVia-Backside Power Delivery
Xiaofei Wang1, Yusung Kim1, Gwang Hyeon Baek1, Kunal Girish Bannore1,
Kaushal Dave1, Arash Joushaghani1, Narae Kang1, Minwoo Ko1, Anandkumar Mahadevan Pillai2, Hema Chandra Prakash Movva1, Gyusung Park1, Muktadir Rahman1, Seenivasan Subramaniam1, Vinay Vashishtha1, Teng Yang1, Zheng Guo1,
ISSCC 2025 Session 29 Memory
A 3nm FinFET 2.2Gsearch/s 0.305fJ/b TCAM with Dynamically Gated Search Lines for Data-Center ASICs
Sushil Kumar*1, Gajanan Jedhe*1, Chetan Deshpande*1, Agastya Gogoi1,
classification and forwarding are fundamental tasks for data-center network (DCN) components, such as switches and routers, which are used to efficiently manage and direct network traffic. Packet classification involves
Phoebe Su2, Kim Soon Jway3, TzeYing Seoh3 MediaTek, San Jose, CA Media
ISSCC 2025 Session 29 Memory
A 38Mb/mm2 380/540mV Dual-Rail SRAM in 3nm-FinFET Technology its leakage is eliminated and INCM returns to VDDA to stop P1 leakage. When opaque LCLKT is at VDDA and the cross-coupled NMOS/PMOS latch is enabled; input switching does not propagate to the output until the latch is transparent.
Harold Pilo1, John Barth1, Kapil Dev Dwivedi2, Peter Lee3, Vikram Kumar2,
Prasanna Nalawar4, Yogeshbhai Patel2, Shailendra Sharad2, Shakti Singh2 A clock buffer with high-voltage LS bypass is shown in Fig. 29.4.3, its design supports an extended voltage range when a large forward split is appl
ISSCC 2025 Session 29 Memory
A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme
Hidehiro Fujiwara1, Wei-Chang Zhao1, Kinshuk Khare1, Yi-Hsin Nien1, Chih-Yu Lin1,
Cheng-Han Lin1, Shan-Ru Liao1, Kenta Torigoe2, Shirleen Xia3, Yuichiro Ishii3, Yao-Yi Liu1, Jhon-Jhy Liaw1, Yen-Huei Chen1, Hung-Jen Liao1, Tsung-Yung Jonathan Chang1 TSMC, Hsinchu, Taiwan TSMC Design Technology Japan, O
ISSCC 2025 Session 3 Analog Circuits
A 36V Current-Balancing Instrumentation Amplifier with ±24V
Input Range, 5.6MHz BW, and 140dB CMRR at All Gain Settings
amplifiers (HV-IAs) are employed to process millivolt-level signals from sensors and standardized 4-to-20mA current signals from transmitters [1,2]. The latter are converted into voltage signals up to 10V via a 250Ω or 5
Shen Ye, Minge Jiang, Jiahao Wang, Shiqi Zhang, Peng Cao, Zhiliang Hon
ISSCC 2025 Session 3 Analog Circuits
A Passive Switched-Capacitor-Based Multimode Amplifier with a Logarithmic Conformity Error of 0.75% from -25 to 200°C
Hendrik Siemssen1, Rochus Nowosielski2, Holger Borchardt2, Jan Mueller2, Bernhard Wicht1
requires integrated electronics to endure harsh environments with temperatures up to 200°C. Acoustic sensors (e.g., piezoelectric) detect environmental composition, as illustrated in Fig. 3.3.1 (top). Due to the natural
Leibniz University Hannover, Hannover, Germany Baker Hughes, Celle, Ge
ISSCC 2025 Session 3 Analog Circuits
A CMOS Operational Amplifier Achieving ±5.8µV 3σ Offset and ±88nV/°C 3σ Offset Drift Using an On-Chip Heater-Based Self-Trimming Technique
In step three, the heater heats up M1,2 and the constant gm biasing circuit together to Thigh, resulting in an offset dr
important that the corresponding D0IDAC1vos code is used to ensure the opamp offset at Troom remains zero. Aodong Zhang1, Mingtao Zhan1, Mengying Chen2, Yi Zhong1, Lu Jie1, Nan Sun1, Qinwen Fan2 The trimming accuracy is
ISSCC 2025 Session 30 Memory
A 28Gb/mm2 4XX-Layer 1Tb 3b/cell WF-Bonding 3D-NAND Flash with 5.6Gb/s/pin IOs
Sang-Soo Park, Jae-Doeg Lyu, Myungjun Kim, Jaeyun Lee, Younsun Song,
Chung-Ho Yu, Hirano Makoto, Yongseok Kwon, Jong-Hoon Park, Ho-Joon Kim, Daein Lee, Donghyun Seo, Byungrok Go, Seoyoon Jeon, Yoonjee Kim, Doo-Hyun Kim, Youngmin Jo, Hyunjun Yoon, Junehong Park, Inmo Kim, Sunghoon Kim, Hok
ISSCC 2025 Session 30 Memory
A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-EnergyEfficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os
Kosuke Yanagidaira1, Mario Sako1, Yasuhiro Hirashima1, Junya Matsuno1,
Yumi Higashi1, Yutaka Shimizu1, Akihiro Imamoto1, Kazuaki Kawaguchi1, Koji Tabata1, Takeshi Nakano1, Yusuke Ochi1, Hiroaki Hoshino1, Takeshi Hioka1, Shigehito Saigusa1, Hiroki Date1, Masaki Unno1, Jumpei Sato1, You Kamat
ISSCC 2025 Session 30 Memory
A 24Gb 42.5Gb/s GDDR7 DRAM with Low-Power WCK
Distribution, an RC-Optimized Dual-Emphasis TX, and, Voltage/Time-Margin-Enhanced Power Reduction
Sang-Hoon Kim, Jaehyeok Baek, Moon-Chul Choi, Daewoong Lee, Donggun An, Se mi Kim, Yeonggeun Song, Minkyo Shim, Sung-Yong Cho, Dongha Lee, Gunhee Cho, In-Woo Jun, Juseop Park, TaeYoon Lee, Hwan-Chul Jung, Chanyong Lee, G
ISSCC 2025 Session 30 Memory
A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5th-Generation 10nm DRAM Process
Jin-Hyeok Baek, Jang-Hoo Kim, Yoo-Chang Sung, Jae-Woo Jeong,
Jin-Kwan Park, Hyun-Kyu Oh, Bo-Hyeon Lee, Dong-Wan Ko, Tae-Seob Oh, Seung-Gi Hong, Chang-Ki Kwon, Daihyun Lim, Myeong-O Kim, Seung-Jun Bae, Tae-Young Oh, Sang-Jun Hwang Samsung Electronics, Hwaseong, Korea The rapid grow
ISSCC 2025 Session 30 Memory
A 321-Layer 2Tb 4b/cell 3D-NAND-Flash Memory with a 75MB/s Program Throughput
Wanik Cho1, Chanhui Jeong1, Jongwoo Kim1, Jongseok Jung1, Keunseon Ahn1,
Jayoon Goo1, Sangkyu Lee1, Kayoung Cho1, Tei Cho1, Dauni Kim1, Gwan Park1, Yushin Ahn1, Sooyeol Chai1, Gwihan Ko1, Sunyoung Jung1, Eunwoo Jo1, Taehun Park1, Jinhyun Ban1, Cheoljoong Park1, Jae Hyun Park1, Sanghoon Oh1, S
ISSCC 2025 Session 30 Memory
A 64Gb DDR4 STT-MRAM Using a Time-Controlled Discharge-Reading Scheme for a 0.001681μm2 1T-1MTJ Cross-Point Cell
Kosuke Hatsuda1, Katsuhiko Hoya1, Ryousuke Takizawa1, Fumiyoshi Matsuoka1,
Takaya Yasuda1, Akira Katayama1, Tadashi Miyakawa1, Kazuyo Senju1, Kazuki Okawa1, Yuka Furukawa1, Yu Shimada1, Katsuya Kotake1, Sayaka Hirokawa1, Min Chul Shin2, Dong Keun Kim2, Tae Ho Kim2, Kyunghoon Kim2, Hisanori Aika
ISSCC 2025 Session 31 Power Management
An Inductor-less Capacitor-less Synchronous PiezoelectricElectromagnetic Hybrid Energy Harvesting Platform with Coil-Sharing Scheme
Yuchen Wei*1, Xinling Yue*1, Zhiyuan Chen2, Sijun Du1
Fudan University, Shanghai, China 1 2 *Equally Credited Authors (ECAs) Along with the rise of the Internet of Things (IoT) and edge artificial intelligence (AI), energy harvesting provides a promising sustainable power s
Delft University of Technology, Delft, The Netherlands
ISSCC 2025 Session 31 Power Management
A Biased-SECE Interface for Piezoelectric Energy Harvesting with Geometric-Mean-Computational MPPT Achieving 99.9%
MPPT Efficiency, 8.75Cycles/∆VOC Tracking, and 9.3x Energy, Extraction
harvesting (PEH)—which converts ambient vibrations into electrical energy—has emerged [1–6]. The interface circuit in a PEH system plays a crucial role not only in energy extraction and conversion but also in enabling th
Jiho Lee, Hyun-Sik Kim KAIST, Daejeon, Korea As the demand for sustain
ISSCC 2025 Session 31 Power Management
A Rectifier-less Piezoelectric Energy-Harvesting Interface with a Sense & Track MPPT Achieving Single-Cycle Convergence and 568% Shock Power Improvement
Shunmin Jiang*1, Xinling Yue*1, Yuchen Ma1, Chao Wang2, Sijun Du1
Huazhong University of Science and Technology, Wuhan, China 1 2 *Equally Credited Authors (ECAs) The number of edge sensors for the Internet-of-Things (IoT) has been increasing dramatically every year to feed servers and
Delft University of Technology, Delft, The Netherlands
ISSCC 2025 Session 31 Power Management
A 91.25% Peak Power-Conversion-Efficiency Capacitive PowerManagement IC Supporting up to 5.68mJ Burst Energy Delivery Using a Single External Capacitor for mm-Scale IoT Applications
Qishen Fang1, Feiyu Li1, Rui P. Martins1,2, Man-Kay Law1
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 As Internet of Things (IoT) devices continue to shrink in size, the limited available system energy is becoming a major bottleneck. Even though the sy
University of Macau, Macau, China