2026

span (100Gauss) Ultra-fast scan (1400THz/s) EPR-on-a-Chip based on injection-locked phase detection, implemented in CMOS 22nm-FDSOI technology is presented. 14GHz coherent frequency generation and sensing signal down-con

Abstract The paper presents a 256-channel solid-state nanopore readout IC in 65nm CMOS. A new integrate-and-hold TIA cuts per-pore power and area >6× while achieving 1MHz BW and 193pArms at 10nA. Event detection with dyn

Abstract Lab-on-CMOS platforms require joint sensing–manipulation capabilities for biosamples from single cells to organoids. Existing methods such as DEP, optical, and acoustic tweezers need external setups, continuous

California, Los Angeles, CA, Kyushu University, Fukuoka, Japan 1 5 Abstract This paper presents a 0.62g light-weight battery-less sensor tag for continuous monitoring of plant stress. A wireless link at 920MHz powers the

*Equally Credited Authors (ECAs) Abstract A hydrogel-based single-culture dual-fluorescence sensor is presented for bioavailable phosphorus (P) detection. The sensor achieves 6.6fA sensitivity with a 15.5dB SNR and an ou

Abstract A highly integrated SoC incorporates ECG, PPG, GSR, and ECH biosignal acquisition interface circuits with a 920MHz, 2kb/s, 1.1µW WuRx, a 2.4GHz, 1Mb/s Tx, and a PMU with <5μs recovery time under 600μA-to-50mA lo

Abstract This work presents continuous, unobtrusive, and clinically accurate BP monitoring in a fully wearable form factor using an near-field RF reflection TRx ASIC in 65nm CMOS. The NRR approach enables noncontact moni

*Equally Credited Authors (ECAs) 1 Abstract This work presents a battery-powered hybrid resonant pulse-train generator for ultrasonic wireless power transfer (US-WPT) in implantable medical devices. The ASIC integrates a

Abstract An ultrasound powering TX ASIC for brain implants with autonomous on-chip standingwave peak tracking for RX power (PDL) regulation is presented. With a proposed adiabatic power-sensing scheme, the TX consumes 43

Abstract A single-link wireless power and full-duplex data transfer system is presented. Operating at 40.68MHz, it delivers >50mW maximum output power with 61.1% peak end-to-end efficiency while supporting 17Mb/s uplink

China, 3Xiaomi, Beijing, China, 4Peking University, Beijing, China 1 Abstract Conventional FP-CIMs suffer from fixed preserved bit-width (PBW), limiting their adaptability and efficiency. This work proposes the first MXF

2University of Chinese Academy of Sciences, Beijing, China Columbia University, New York, NY *Equally Credited Authors (ECAs) 1 3 Abstract Previous non-volatile CIM (nvCIM) macros suffer from low storage density, unneces

Jen-Chun Tien1, De-Qi You1, Ping-Sheng Wu2, Bo Zhang3, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Meng-Fan Chang1,2 National Tsing Hua University, Hsinchu, Taiwan, 2TSMC Corporate Research, Hsinchu, Taiwan, 3TSMC

Abstract This paper proposes a bit-parallel digital CIM macro featuring a lossless compressor based on transition-counting-lines (TCLs) for bit-column addition. The bus TCL incorporates signbit extension to support signe

Yao-Kai Yeh1, De-Qi You1, Ashwin Sanjay Lele3, Brian Crafton3, Bo Zhang3, Ping-Sheng Wu2, Ya-Tang Yang1, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Meng-Fan Chang1,2 National Tsing Hua University

2University of Chinese Academy of Sciences, Beijing, China Columbia University, New York, NY *Equally Credited Authors (ECAs) 1 3 Abstract Previous near-memory computing (NMC) or in-memory-computing (IMC) NANDs suffers f

Sciences, Beijing, China, 3Zhangjiang Laboratory, Shanghai, China Xi’an UniIC Semiconductors, Xi’an, China 1 4 Abstract A high-bandwidth-density (12.77GB/s/mm2) high-memory-density (99.4Mb/mm2) lowenergy-consumption (0.6

System, Hong Kong, China, 3Hefei Reliance Memory, Hefei, China, Zhejiang University, Hangzhou, China 1 4 Abstract This work presents a 55nm speculative decoding-based LLM accelerator with bumpingbased face-to-face ReRAM-

Abstract Revolver is a low-bit GenAI accelerator that enables reasoning and multi-turn chat on edge devices under tight memory and power budgets. It introduces Phase-Aware Precision Selection (PAPS) with Multi-Precision

Abstract A 51.6μJ/token accelerator for rotation-based dual-quantized LLMs is presented. A subspace-rotation method with parallel Hadamard transposer reduces on-chip rotation power by 62.3% and area by 59.7%. A fused sca

Abstract This paper presents VARSA, a 22nm visual autoregressive accelerator for efficient text-toimage generation, featuring: 1) a performance-scalable hybrid PE-LUT core; 2) multi-precision parallel processing with run

Abstract This work presents SoulMate, a fully on-device mobile intelligence system-on-chip, integrating retrieval-augmented generation (RAG) and fine tuning of a personal LLM. SoulMate is fabricated in 28nm CMOS with a n

Abstract This paper presents Tri-Oracle, a VLM accelerator exploiting token, attention, and weight redundancies. A Token Merging Unit (TMU) merges 68% of redundant tokens. An Attention Head Prediction Unit (AHPU) predict

Ulsan National Institute of Science and Technology, Ulsan, Korea, 4Naver Cloud, Seongnam, Korea *Equally Credited Authors (ECAs) 1 3 Abstract State-space models (SSMs) and weight-only quantization alleviate huge external

Abstract LLMs face decoding bottlenecks. Speculative Decoding (SD) reduces latency via a small draft model for serial decoding and a large target model to verify in parallel. Despite this advantage, it still suffers from

Qijing Huang1, Shalini De Mello1, Brucek Khailany2 Nvidia, Santa Clara, CA, 2Nvidia, Austin, TX, 3Nvidia, Durham, NC, 4Stanford University, Stanford, CA 1 Abstract ALPhA-Vision is an always-on low-power subsystem for DNN

Abstract This paper presents a 98.5dB SNDR, 250kHz bandwidth CT incremental Zoom ADC. The design features a chopped capacitive front-end, Gm-C residue integrator, and 10b SAR ADC. A smart-tracking (ST) technique with dyn

Abstract A fully dynamic calibration-free ΔΣ ADC using capacitive-degeneration integrators with bottom-plate level shift (BPLS) is presented. BPLS samples negative charge to reduce threshold-voltage dependence, improve s

Abstract This paper presents an incremental pipeline ADC with dual-residue architecture. An exponential ΔΣ loop is proposed to directly quantize the residue, replacing conventional interpolators that are complex and less

Abstract This paper presents a quadratic-exponential noise-coupled (NC) IDSM to achieve a quantization noise shaping effect greater than 4th order with OSR 22, while having high tolerance to DAC non-linearity and a small

Abstract This paper presents a mm-wave non-magnetic balanced circulator that bridges the gap between the high insertion loss (IL) of electrical balance duplexers and the transmitter (TX)to-receiver (RX) isolation degrada

Abstract This work presents a balanced power amplifier (PA) featuring a time-varying output matching network designed to suppress unwanted reflections and couplings in phased array and MIMO systems. By leveraging lossy n

*Equally Credited Authors (ECAs) Abstract A 6GHz quadrature DTX supporting a 1GHz signal bandwidth is presented in 28nm CMOS, where static and dynamic nonlinearities are carefully optimized. Occupying a core area of 0.67

Abstract This work presents a switched-capacitor power amplifier (SCPA) using periodic voltagepacing network, capable of generating output voltage beyond conventional rail-to-rail limit, which enhances both the output po

Abstract A 2&4 phased-array SIL radar-on-chip in 22nm CMOS is demonstrated for in-cabin vitalsign monitoring. Built on a forward-ΔΣ DPLL-locked multi-injection RTWO at 20GHz, it concurrently serves as (de)modulator, beam

Abstract We present a 234-to-252GHz dual-polarized monostatic CMOS (Intel16) transceiver for cross-polarimetric sensing, with antenna-in-package (AiP) technology and a 10&10mm2 modular system assembly. The AiP achieves 6

Lianbo Wu1,2, Guangzhong Zhang3, Naike Du3, Zijie Wang1, Yucong Gu1, Xiuzhu Ye3, Xiao Fang1, Weisheng Zhao1,2, Hui Zhang1,2 Beihang University, Beijing, China, 2Tianmushan Laboratory, Hangzhou, China, 3Beijing Institute

Abstract This work presents an IEEE 802.15.4a/z/ab compatible IR-UWB TX using an anti-phase delayed dual-Gaussian pulse with self-delay pulse comb-notch to maximize the spectrum utilization while meeting global masks. A

Abstract This paper presents a system that breaks the trade-off between range and power present in conventional wireless backscatter systems caused by phase noise leakage at low intermediate frequencies (IFs). By employi

crystal-less localization tag with a 28nm TX IC, custom antenna, PV cells, and storage cap achieves 0.9m accuracy over 1.45km. Designed for tracking wasps, this system also enables unobtrusive monitoring of other small i

052mm2 blocker-tolerant 18-to-22GHz non-uniform current subsampling (NUCSS) receiver featuring NU DT FIR/IIR filtering and equalized Gm-cells, addressing aliasing, noise folding, and alias/non-alias band blockers. Fabric

0-compliant dual-band RF transceiver. Compared with traditional BT/BLE counterparts, this design achieves receiver figures of merit (FOM) of 188.7dB in the 2.4GHz band and 185.2dB in the 5GHz band, exceeding the state-of

Abstract A sub-μW fully integrated backscattered 802.11b WiFi transmitter is introduced with active image and harmonics rejection for common dense wireless environments. Rejection is achieved via time-domain complex filt

Abstract This work presents ReFIND, an SoC integrating together 16 resolution-reconfigurable AFEs, a feature extractor, and a classifier. The VCO ADC architecture trades power for resolution by scaling the integration ti

*Equally Credited Authors (ECAs) 1 Abstract This paper presents a frame-rate-scalable duty-cycled electrical impedance tomography system to reduce average power consumption. A proposed multiple-input multiple-output curr

Abstract This paper presents a fast impedance-measurement IC for large-scale piezo-resistive sensor arrays. It features a unified differential time-to-digital demodulation architecture that reads out impedance directly t

*Equally Credited Authors (ECAs) 1 Abstract This work presents a 65nm ExG SoC for smart glasses, enabling low-power neural interaction. A 10-ch AFE and on-chip CNN deliver real-time EOG/EMG/EEG inference. Ondevice contin

Abstract We present a patient-independent, prototype-based spatio-temporal CNN processor for seizure detection, achieving high accuracy without patient-specific data, at an energy of 16.4nJ/class and latency of <120ms. A

Shijiazhuang, China National Tsing Hua University, Hsinchu, Taiwan *Equally Credited Authors (ECAs) 1 4 Abstract This paper reports an olfactory processor with on-chip transfer learning for cross-hospital and cross-pulmo

Abstract To enable high-fidelity wearable ExG acquisition, this paper presents an NS-SAR ADC that performs 2nd-order shaping of both quantization and kT/C noises through a multi-tasking integrator (MTI) and loop dynamics