2026

Chinese Academy of Sciences, Beijing, China, 4Soochow University, Suzhou, China *Equally Credited Authors (ECAs) 1 3 Abstract This 1024-electrode neural interface solves the power, area, and bandwidth bottleneck by combi

Abstract This work presents a hybrid optogenetic stimulation system with sub-threshold electrical stimuli that lower the optical threshold and reduce energy consumption. It achieves 90.75% LED driving efficiency through

Abstract We propose a light-adaptive retinal prosthesis (LARP) SoC, which employs power-aware light adaptation achieving a wide light-sensing DR of 55.48dB. Pixel clustering enables a compact pixel size of 80×80μm2, enha

Harrie A. C. Tilmans, Anabel De Proft, Barundeb Dutta, Carolina Mora Lopez imec, Heverlee, Belgium *Equally Credited Authors (ECAs) Abstract We present a waveguide-based optogenetics neural probe with 1,280 electrodes, 3

Abstract This paper presents a 72Gb/s/pin PAM-3 single-ended transceiver in 28nm CMOS. Drivercooperative coding enhances signal integrity and reduces signaling power by ≥46%. Asymmetric data-dependent equalization and bi

Interdisciplinary Research Center for Future Intelligent Chips (Chip-X), Suzhou, China 1 3 Abstract This paper presents a five-lane 112Gb/s/pin PAM4 single-ended transceiver in 28nm CMOS for high-density short-reach memo

LPDDR6 PHY that achieves 14.4Gb/s/pin, increasing bandwidth while optimizing power. Key innovations include quadrature clocking, with QEC, to reduce jitter sensitivity, and a multi-level FIFO-based speculative DFE to rel

*Equally Credited Authors (ECAs) 1 Abstract A 16Gb/s/pin 0.51pJ/b single-ended NRZ transceiver with distributed dual-loop compensation (DDLC) for VDDQ-ripple suppression and dynamic duty-cycle calibration (DDCC) for robu

*Equally Credited Authors (ECAs) Abstract We present a cross-self-referenced slope-sampling RX that is robust against long-tail ISI, without equalization, for next-generation low-power memory interfaces. By determining r

8Gb/s/pin receiver with a one-way self-training scheme for highlyreflective multi-drop memory interfaces. DFE tap coefficients are directly derived from a single-pulse response, eliminating controller interaction during

Abstract This work presents a 0.87pJ/b, 17Gb/s/pin parallel receiver with local DQS recovery and a dual-DQS tree for reduced clock power and mitigated power supply-induced jitter (PSIJ). The local DQS recovery time-multi

Abstract This paper presents a compact 14Gb/s/pin HBM DQ receiver that continuously tracks sampling phase and detector offset in live data, using a baud-rate phase tracking loop with a background-calibrated time-window p

Abstract This paper presents a CMOS bandgap reference (BGR) with a current-domain high-order TC compensation by using a capacitively-biased-diode-based super-PTAT current bias. It achieves a TC of 2.1 to 7.1ppm/°C from -

Abstract This paper presents a process-independent, curvature-compensated bandgap reference. By introducing a temperature-adaptive duty-cycled resistor to scale the PTAT voltage, the design effectively compensates for CT

Abstract This work implements an integrated voltage and current reference circuit, which has low temperature drift. By ensuring the reuse of the main circuit, we propose a current-mirrorbased seamless transition techniqu

Japan, 4Iwate University, Iwate, Japan 1 Abstract Conventional satellites are costly and unreliable. We propose a pico-satellite formation as a virtual phased array to reduce costs and improve reliability. A low-power FD

Abstract Prior works on physical-layer eavesdropping protection only addressed off-axis Eve. This paper presents the first TX to defend against both main-beam and off-axis Eves. Incorporating three key components: freque

Abstract This paper presents a 140GHz CMOS transceiver for both full-duplex and frequency-division duplex communication. By proposing self-interference (SI)-cancelling antenna and dualpolarized metasurface, the design ac

Abstract We present a novel RF canceller that utilizes (i) a novel N-path-filter-based architecture that uses filter stacking to achieve passive tap combining leading to a lower NF degradation, (ii) a sub-cycle rotation

Abstract This paper presents a phased-array-inspired RF signal processor for ultra-broadband spectrum sensing. The proposed architecture exploits the bandpass response resulting from the constructive and destructive inte

Abstract This work presents an ultra-compact 10GS/s sampled beamforming (BF) receiver front-end (FE) for a 2×2 antenna array, enabling both azimuth and elevation steering in 22nm FDSOI CMOS. The 4× time-interleaved FE fe

Abstract This paper presents a 436-to-472GHz 4-element IF beamforming phased-array receiver in 65nm CMOS. A two-step mixing architecture reduces layout overhead. The LO frequency multiplier chain provides >-1dBm over 180

25-to-29.5 / 37-to-40GHz fully connected MIMO receiver (RX) front-end for 5G FR2 that enables 52-to-70dB calibration-free inter-band blocker rejection and up to -5dBm blocker tolerance is introduced. A compact on-chip di

Duncan Hall1, Axel Crocherie1, Cedric Pastorelli1, Sophie Taupin2, Severin Trochut2, Abhishek Singh1, Andreas Assmann1, Bruce R. Rae1, Pascal Mellot2 STMicroelectronics, Edinburgh, United Kingdom, 2STMicroelectronics, Gr

Abstract We propose a 200MP 0.61µm pixel size CMOS image sensor featuring: 1) an interlacedshared pixel architecture to achieve a 0.7e- readout noise, 2) an on-chip motion artifact-free HDR synthesis with single-frame dy

*Equally Credited Authors (ECAs) 1 Abstract VoxCAD, an intelligent low-power dToF SoC for end-to-end 3D perception applications, is presented with three features: 1) LiDAR dToF sensing-integrated 2D-ROI guided point clou

*Equally Credited Authors (ECAs) 1 Abstract A 480×320 CMOS LiDAR sensor using tapered 1-step hTDCs and SPER for memory-efficient operation is presented. The hTDC accumulates histograms with 1ns resolution over the full r

Sony Semiconductor Solutions Europe, Trento, Italy, 2Sony Semiconductor Solutions, Atsugi, Japan 1 Abstract This paper presents a 400×300-pixel Ge-SPAD SWIR/NIR sensor enabling very-low-power operation: the flexible macr

*Equally-Credited Authors (ECAs) Abstract This paper presents a 128×96 multimodal flash LiDAR SPAD imager integrated with a compute-near-sensor Ising-model annealing processor for dynamic object segmentation, framed as a

Abstract This paper presents a fully reconfigurable HDR intensity/event hybrid SPAD sensor. The fully reconfigurable scheme enables both pixel types to be freely blended and operated simultaneously. A time-coded dual exp

presents a fully analog intelligent vision SoC that eliminates both sensorprocessor and inter-layer A/D conversions for end-to-end vision. A continuous analog datapath from sensing to multi-layer inference is enabled by

Gihwan Cho, Hyukbin Kwon, Jaehun Jeong, Bumjun Kim, Su-Hyun Han, Youna Lee, Hiroyuki Sugihara, Junghoon Jung, Suksan Kim, Kyungtae Lim, Wonoh Ryu, Yongjun Kim, Seung-Sik Kim, Heesung Shim, Min-Woong Seo, Jae-kyu Lee, Jon

work demonstrates a UCIe-S compliant die-to-die PHY at 48Gb/s/lane across 16 lanes, achieving 1.24Tb/s/mm shoreline BW density over a 30mm organic package at 1.2pJ/b, extendable to 56GT/s (1.13pJ/b). Circuit innovations

Abstract This paper presents a 180-240Gb/s analog-intensive PAM-4 transmitter in 65nm CMOS process. A three-stage cascaded 2-to-1 analog MUX (AMUX) is employed to reduce the complexity and therefore the parasitic capacit

Abstract A resistor-less 7b SST DAC-based TX with 8-tap FFE and 3 types of segments is presented to achieve low parasitic capacitance, compact area, and scaling friendliness. To reduce intersymbol-interference jitter at

Chin-Hua Wen1, Hsin-Hung Kuo1, Han-Tzung Ke1, Jie-Ren Huang1, Chang-Yi Li1, Sheng-Tsung Lai1, Shu-Chun Yang1, Kuan-Ting Chou1, Pei-Chen Chiou1, Tsung-Hsien Tsai1, Yi-Ting Chen1, Yen-Ming Chen1, Kenny Cheng-Hsiang Hsieh1

Marina Salik2, Kevin Bartholomew2, Sushmitha Reddy2, Alex Tessitore2, Aws Shallal2, Kalyan Nallaparaju2, Jin Liang2, Minhan Chen2, Shaishav Desai1 Microsoft, Sunnyvale, CA, 2Microsoft, Raleigh, NC 1 Abstract This work pr

*Equally Credited Authors (ECAs) 1 Abstract This work presents an 8-lane 112Gb/s/wire single-ended simultaneous bi-directional transceiver with a 3mm shield-less on-chip channel. A dynamic equalizer is proposed to decoup

*Equally Credited Authors (ECAs) 1 Abstract This paper presents a 112Gb/s mixed-signal reference-less PAM-4 CDR in 28nm CMOS. By proposing the hybrid architecture based on a symmetrical linear PD and a bang-bang PFD, a f

Alberto Grassi1, Mehrdad Fahimnia1, Hiroshi Kimura2, Faramarz Bahmani2, Hao Chen2, Alex Wang2, Chen Zhao2, Yuan Fang2, Allen Chen3, Afshin Momtaz1, Namik Kocaman1 Broadcom, Irvine, CA, 2Broadcom, San Jose, CA, 3Broadcom,

Abstract A 112Gb/s PAM-4 simultaneous bidirectional (SBD) transceiver in 28nm CMOS is presented. It features a hybrid with a 2×VDD stacked driver to restore signal swing, a joint delay and slew-rate matching scheme to el

Abstract A low-power (0.292pJ/b), high-bandwidth (56Gb/s/wire) single-ended capacitively driven simultaneous bi-directional (CD-SBD) TRX with PVT tolerance is proposed. Capacitive driving reduces power and self-interfere

Abstract This paper presents a 72Gb/s/pin single-ended simultaneously bi-directional (SBD) TRX in 28nm CMOS. Capacitive peaking leakage cancellation (CPLC) suppresses the high-frequency leakage due to the main and hybrid

Abstract A 13.56MHz wireless power and data transfer (WPDT) system for implantable voltammetry sensor is presented. With the synchronized phase-shifted time-multiplexing technique, the system uses a single power link to

Abstract A bipolar quad-output regulating rectifier for wireless power transfer (WPT) is presented. Using only five power switches, it provides four independently regulated bipolar outputs. A coil-reused DC-DC mode susta

Abstract This paper presents an output-domain-independent single-transmitter-dual-receiver wireless power transfer system. The proposed detuned-tank and time-multiplexing control enable adaptive power distribution, preve

Abstract This work presents a system-level scalable wireless power receiver (RX) network for miniaturized distributed somatosensory cortex stimulation. By interconnecting the power outputs of all RX cells in the network,