机构

Hitachi

4 篇 ISSCC 论文

ISSCC 2019 Session 2 AI / ML
A 2×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems
Takashi Takemoto1, Masato Hayashi2, Chihiro Yoshimura2, Masanao Yamaoka2
computer architecture, commonly known as annealing processor [1, 2]. An annealing processor provides a fast means for finding the ground state of an Ising model; thus, it can efficiently solve NP-hard combinatorial optimiz
Hitachi, Sapporo, Japan Hitachi, Tokyo, Japan 1 2 The last decade has
ISSCC 2009 Session 7 Memory
Low-Vt Small-Offset Gated Preamplifier for Sub-1V Gigabit DRAM Arrays
Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh
achieves fast sensing, fast local I/O driving and low-leakage operation simultaneously even for low-voltage mid-point sensing. The features are verified with a 70nm 128Mb DRAM core that demonstrates 16.4ns row access (tR
Hitachi, Kokubunji, Japan A sensing scheme with temporary activation o
ISSCC 2009 Session 29 mm-Wave
A 59GHz Push-Push VCO with 13.9GHz Tuning Range Using Loop-Ground Transmission Line for a FullBand 60GHz Transceiver
Takahiro Nakamura, Toru Masuda, Katsuyoshi Washio, Hiroshi Kondoh
60GHz wireless communication systems, using the unlicensed frequency band from 57 to 66GHz, are expected to make high-data-rate transfer possible. IEEE 802.15.3c is finalizing a radio-frequency (RF) allocation composed o
Hitachi, Kokubunji, Tokyo, Japan
ISSCC 2008 Session 26 Wireless
A 28GHz Low-Phase-Noise CMOS VCO Using an Amplitude-Redistribution Technique
Yusuke Wachi, Toshiyuki Nagasaku, Hiroshi Kondoh
Increasing demands for multi-Gb/s data transmission make the mm-wave wireless communication systems more attractive. The VCO is an essential block in these systems. This paper describes an amplitude-redistribution techni
Hitachi, Tokyo, Japan