Low-Vt Small-Offset Gated Preamplifier for Sub-1V Gigabit DRAM Arrays

📋 论文概要

本文提出一种低Vt门控前置放大器（LGA）与高Vt读出放大器并联的传感方案，实现了亚1V千兆位DRAM阵列的快速传感、快速本地I/O驱动和低泄漏操作。在70nm 128Mb DRAM核心上验证，在0.9V阵列电压下获得16.4ns行访问和14.3ns读取访问。

💡 主要创新点

• 提出低Vt门控前置放大器（LGA）与高Vt读出放大器并联结构，同时实现快速传感和低泄漏。
• 通过降低MOSFET阈值电压变化和读出放大器失调电压，提升低电压下的传感裕度。
• 在0.9V低电压下实现16.4ns的快速行访问，验证了方案的有效性。

🏷 关键词

📄 原文摘要

achieves fast sensing, fast local I/O driving and low-leakage operation simultaneously even for low-voltage mid-point sensing. The features are verified with a 70nm 128Mb DRAM core that demonstrates 16.4ns row access (tRCD) and 14.3ns read access (tAA) at an array voltage of 0.9V. The LGA is promising for future sub-1V gigabit DRAMs because it reduces variation in threshold voltage (Vt) of MOSFETs and in the offset voltage of sense amplifiers. The sensing scheme with a low-Vt gated preamplifier (LGA) connected in parallel to a high-Vt sense amplifier (SA) is shown in Fig. 7.8.1. The LGA quickly amplifies an initial cell signal (vS0) because of its low Vt, despite the mid-point sensing, by turning on a high-Vt sense gate (SG) to a level (vS1) higher than the offset voltage of the high-Vt SA. Then, vS1 is further amplified by subsequent activation of the SA to a latch level (vS2) for

👥 作者与机构

Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh

Hitachi, Kokubunji, Japan A sensing scheme with temporary activation of a low-Vt gated preamplifier (LGA)