ISSCC 2018
Session 16
Wireline I/O
A 7.8Gb/s/pin 1.96pJ/b Compact Single-Ended TRX and CDR with Phase-Difference Modulation for Highly Reflective Memory Interfaces
strongly demanded by the memory industry. Although discontinuous reflective channels like multi-drop DRAM interfaces are less suitable for high data rates than continuous point-to-point channels, their great advantages i
ISSCC 2017
Session 5
Analog Circuits
A 9.3nW All-in-One Bandgap Voltage and Current Reference Circuit
have presented challenges in ULP implementation of reference circuits while keeping traditional requirements of stable performance. For voltage reference circuits, as an essential block in SoCs to generate various intern
ISSCC 2014
Session 2
Wireline I/O
A Coefficient-Error-Robust FFE TX with 230% EyeVariation Improvement Without Calibration in 65nm CMOS Technology
(FFE) transmitter (TX) for massively parallel links. Recently, massively parallel links such as on-chip links [1-3], silicon interposers [4,5], or wide I/Os [6] are gaining popularity to meet increasing demand for data t