ISSCC 2022
Session 29
AI / ML
A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes
state-of-the-art results in many fields, like natural language processing and computer vision, but their large number of matrix multiplications (MM) result in substantial data movement and computation, causing high laten
ISSCC 2022
Session 15
AI / ML
A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration
have been proposed for edge deep learning (DL) acceleration. They usually rely on analog CIM techniques to achieve highefficiency NN inference with low-precision INT multiply-accumulation (MAC) support