A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration

📋 论文概要

该论文提出了一款28nm工艺的可重构数字计算存储（CIM）处理器，支持BF16和INT8精度，采用统一的浮点/整数流水线架构，实现了29.2 TFLOPS/W和36.5 TOPS/W的高能效，解决了模拟CIM精度受限的问题。

💡 主要创新点

• 提出数字CIM架构，避免模拟CIM的噪声和精度问题
• 设计统一的FP/INT流水线，支持混合精度计算
• 可重构配置适应不同神经网络需求

🏷 关键词

📄 原文摘要

have been proposed for edge deep learning (DL) acceleration. They usually rely on analog CIM techniques to achieve highefficiency NN inference with low-precision INT multiply-accumulation (MAC) support

👥 作者与机构

Fengbin Tu1,2, Yiqi Wang1, Zihan Wu1, Ling Liang2, Yufei Ding2, Bongjin Kim2,

Leibo Liu1, Shaojun Wei1, Yuan Xie2, Shouyi Yin1 Tsinghua University, Beijing, China University of California, Santa Barbara, CA 1 2 Many computing-in-memory (CIM) processors