ISSCC 2022

2022

167 篇论文 · AI / ML (23) · Power Management (21) · RF & Wireless (18) · Data Converters (13) · Digital Circuits (12)

ISSCC 2022 Session 10 Data Converters
A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology
Juzheng Liu, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen
High-speed (>GS/s) medium-resolution ADCs are in high demand for wideband communication ICs. Meanwhile, the increasing cost in advanced technology nodes favors area-efficient ADC architectures. The traditional voltage-do
University of Southern California, Los Angeles, CA
ISSCC 2022 Session 10 Data Converters
A 0.82mW 14b 130MS/s Pipelined-SAR ADC with a Distributed Averaging Correlated Level Shifting (DACLS) Ringamp and Bypass-Window Backend
Jia-Ching Wang, Tai-Haur Kuo
To fulfill upcoming communication specifications, it has become popular recently to employ pipelined-SAR architectures, incorporating residue amplifiers (RA) to achieve high resolution, wide bandwidth, and low-power ADCs
National Cheng Kung University, Tainan, Taiwan
ISSCC 2022 Session 10 Data Converters
A 0.004mm2 200MS/s Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp
Mingtao Zhan1, Lu Jie1, Xiyuan Tang2, Nan Sun1
Peking University, Beijing, China 1 2 Pipelined ADCs are widely used for high-speed high-resolution applications, but there are two challenges. First, limited by the kT/C noise requirement, its 1st-stage sampling capacit
Tsinghua University, Beijing, China
ISSCC 2022 Session 10 Data Converters
A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment
Haoyi Zhao, Fa Foster Dai
The pipelined SAR ADC is a promising architecture to achieve high sample rate with high resolution. Residue amplifiers are normally required between pipelined stages to provide sufficient gain for relaxing the noise requ
Auburn University, Auburn, AL
ISSCC 2022 Session 10 Data Converters
A 24b 2MS/s SAR ADC with 0.03ppm INL and 106.3dB DR in 180nm CMOS
Jesper Steensgaard1, Richard Reay2, Raymond Perry2, Dave Thomas2,
for low-to-medium speed applications. The ADC function accommodates a wide range of use, including Nyquistrate data acquisition and oversampled signal applications. The noise spectral density (NSD) is uniform from 0Hz to
Geoffrey Tu2, George Reitsma2 Analog Devices, Sequim, WA Analog Device
ISSCC 2022 Session 10 Data Converters
A 4.96µW 15b Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC
Yuyan Liu1, Menglian Zhao1, Yibo Zhao1, Xiaopeng Yu1, Nianxiong Nick Tan1,
applications, such as smart sensors and event-driven IoT devices, which need ADCs with high resolution, high power efficiency, and can be multiplexed between multiple inputs. Despite these advantages, they usually need a
Le Ye2, Zhichao Tan1 Zhejiang University, Hangzhou, China Peking Unive
ISSCC 2022 Session 10 Data Converters
A 0.014mm2 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR
Lu Jie1, Mingtao Zhan1, Xiyuan Tang2, Nan Sun1
Peking University, Beijing, China 1 2 High-resolution (>100dB SNDR), kHz-BW ADCs are required by emerging IoT and smart sensing applications. These ADCs are desired for their high efficiency, but low cost and ease of int
Tsinghua University, Beijing, China
ISSCC 2022 Session 11 AI / ML
A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations
Yen-Cheng Chiu*1, Chia-Sheng Yang*1, Shih-Hsin Teng1, Hsiao-Yu Huang1,
Fu-Chun Chang1, Yuan Wu1, Yu-An Chien1, Fang-Ling Hsieh1, Chung-Yuan Li1, Guan-Yi Lin1, Po-Jung Chen1, Tsen-Hsiang Pan1, Chung-Chuan Lo1, Win-San Khwa2, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Chieh-Pu Lo2, Yu
ISSCC 2022 Session 11 AI / ML
An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-SpaceReadout with 1286.4 - 21.6TOPS/W for Edge-AI Devices
Je-Min Hung1, Yen-Hsiang Huang1, Sheng-Po Huang1, Fu-Chun Chang1,
Tai-Hao Wen1, Chin-I Su2, Win-San Khwa2, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Yu-Der Chih2, Tsung-Yung Jonathan Chang2, Meng-Fan Chang1,2 National Tsing Hua University, Hsinchu, Taiwan TSMC
ISSCC 2022 Session 11 AI / ML
Single-Mode CMOS 6T-SRAM Macros with Keeper-LoadingFree Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms
Yihan Zhang1, Chang Xue1, Xiao Wang1, Tianyi Liu1, Jihang Gao1, Peiyu Chen1,
Advanced Institute of Information Technology of Peking University, Hangzhou, China 1 2 Miniaturized wireless IoT sensor nodes stay mostly in their standby mode and wake up periodically to sense and store a small amount o
Jinguang Liu2, Linan Sun2, Linxiao Shen1, Jiayoon Ru1, Le Ye1,3, Ru Hu
ISSCC 2022 Session 11 AI / ML
A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computingin-Memory Macro Supporting Wide-Range Dynamic-VoltageFrequency Scaling and Simultaneous MAC and Write Operations
Hidehiro Fujiwara1, Haruki Mori1, Wei-Chang Zhao1, Mei-Chen Chuang1,
Rawan Naous2, Chao-Kai Chuang1, Takeshi Hashizume3, Dar Sun1, Chia-Fu Lee1, Kerem Akarvardar2, Saman Adham4, Tan-Li Chou1, Mahmut Ersin Sinangil2, Yih Wang1, Yu-Der Chih1, Yen-Huei Chen1, Hung-Jen Liao1, Tsung-Yung Jonat
ISSCC 2022 Session 11 AI / ML
A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-LogicBased ADC-less SRAM Compute-In-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications
Bonan Yan1, Jeng-Long Hsu2, Pang-Cheng Yu2, Chia-Chi Lee2, Yaojun Zhang3,
China 4 Duke University, Durham, NC 1 2 Advanced intelligent embedded systems perform cognitive tasks with highly-efficient vector-processing units for deep neural network (DNN) inference and other vector-based signal pr
Wenshuo Yue1, Guoqiang Mei3, Yuchao Yang1, Yue Yang2, Hai Li4, Yiran C
ISSCC 2022 Session 11 AI / ML
A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices
Ping-Chun Wu*1, Jian-Wei Su*2, Yen-Lin Chung1, Li-Yang Hong1,
Jin-Sheng Ren1, Fu-Chun Chang1, Yuan Wu1, Ho-Yu Chen1, Chen-Hsun Lin1, Hsu-Ming Hsiao2, Sih-Han Li2, Shyh-Shyuan Sheu2, Shih-Chieh Chang2, Wei-Chung Lo2, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1
ISSCC 2022 Session 12 Medical & Bio
A 210 × 340 × 50µm Integrated CMOS System for
Micro-Robots with Energy Harvesting, Sensing,
Processing, Communication and Actuation Li Xu1, Maya Lassiter2, Xiao Wu1, Yejoong Kim1, Jungho Lee1, Makoto Yasuda3, Masaru Kawaminami4, Marc Miskin2, David Blaauw1, Dennis Sylvester1 University of Michigan, Ann Arbor, M
ISSCC 2022 Session 12 Medical & Bio
A 200 x 256 Image Sensor Heterogeneously Integrating a 2D Nanomaterial-Based Photo-FET Array and CMOS Time-to-Digital Converters
Henry Hinton1, Houk Jang1, Wenxuan Wu1, Min-Hyun Lee2, Minsu Seol2,
voltage VINT. Upon light illumination, the photocurrent through the drain of the MoS2 photo-FET in a given pixel discharges CP, and a counter records the total number of clock cycles (nCLK), until the voltage across CP r
Hyeon-Jin Shin2, Seongjun Park2, Donhee Ham1 Harvard University, Cambr
ISSCC 2022 Session 12 Medical & Bio
A Self-powering Wireless Soil-pH and Electrical Conductance Monitoring IC with Hybrid Microbial Electrochemical and Photovoltaic Energy Harvesting
Chuan-Yi Wu1, Chi-Wei Liu1, Jing-Siang Chen1, Cong-Sheng Huang1,
Ting-Heng Lu1, Ling-Chia Chen1, I-Che Ou1, Sook-Kuan Lee2, Yen-Chi Chen2, Po-Hung Chen1, Chi-Te Liu2, Ying-Chih Liao2, Yu-Te Liao1 National Yang Ming Chiao Tung University, Hsinchu, Taiwan National Taiwan University, Tai
ISSCC 2022 Session 12 Medical & Bio
A 256-Channel Actively-Multiplexed µECoG Implant with Column-Parallel Incremental ∆Σ ADCs Employing Bulk-DACs in 22-nm FDSOI Technology
Xiaohua Huang1,2, Horacio Londoño-Ramírez1,2,3, Marco Ballini1,4,
Chris Van Hoof1,2, Jan Genoe1,2, Sebastian Haesler1,2,3,5, Georges Gielen1,2, Nick Van Helleputte1, Carolina Mora Lopez1 imec, Leuven, Belgium KU Leuven, Leuven, Belgium 3 Neuroelectronics Research Flanders, Leuven, Belg
ISSCC 2022 Session 12 Medical & Bio
A CMOS Cellular Interface Array for Digital Physiology Featuring High-Density Multi-Modal Pixels and Reconfigurable Sampling Rate
Adam Y. Wang*1, Yuguo Sheng*1, Wanlu Li2, Doohwan Jung3, Greg Junek1,
Jongseok Park4, Dongwon Lee1, Mian Wang2, Sushila Maharjan2, Sagar Kumashi1, Jin Hao2, Yu Shrike Zhang2, Kevin Eggan5, Hua Wang1,6 Georgia Institute of Technology, Atlanta, GA Brigham and Women’s Hospital, Harvard Univer
ISSCC 2022 Session 12 Medical & Bio
A CMOS Molecular Electronics Chip for Single-Molecule Biosensing
University of California, San Diego, CA
Roswell Biotechnology, San Diego, CA metal are exposed by etching away a sacrificial 23µm×15µm “bond pad” to expose a common staging area for the electrodes of 4 adjacent pixels. The 50nm wide electrodes are patterned, t
ISSCC 2022 Session 12 Medical & Bio
1024 3D-Stacked Monolithic NEMS Array with 375µm2 0.5mW 0.28ppm Frequency Deviation Pixel-level Readout for Zeptogram Gravimetric Sensing
Gérard Billiot, Paul Mattei, Bogdan Vysotskyi, Adrien Reynaud, Louis Hutin,
Christophe Plantier, Emmanuel Rolland, Marc Gely, Giulia Usai, Claude Tabone, Gaël Pillonnet, Stéphanie Robinet, Sébastien Hentz CEA-Léti, Grenoble, France NanoElectroMechanical System (NEMS)-based resonator sensors are
ISSCC 2022 Session 13 Digital Circuits
Clock Generator with ISO26262 ASIL-D Grade Safety Mechanism for SoC Clocking Application
Dokyung Lim, Sounghun Shin, Seungmin Lee, Kihyun Kwon, Jeongmin An,
advanced integrated circuits for automotive applications have become stricter than at any other time. ISO26262 (Road Vehicle Functional Safety Standard) determines the risk level associated with systematic and random fai
Wonsik Yu, Chanyoung Jeong, WooSeok Kim, Michael Choi, Jongshin Shin S
ISSCC 2022 Session 13 Digital Circuits
A 0.021mm2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency
Rongjin Xu1, Dawei Ye1, Sirou Li1, C. -J. Richard Shi2
University of Washington, Seattle, WA 1 2 The digital injection-locked clock multiplier (ILCM) using ring oscillators (ROs) is a superior choice for clock generation due to its ease of scaling, compact area, and prominen
Fudan University, Shanghai, China
ISSCC 2022 Session 13 Digital Circuits
Fully Automated Hardware-Driven Clock-Gating Architecture with Complete Clock Coverage for 5nm Exynos Mobile SoC
Jae-Gon Lee, Hoyeon Jeon, Younsik Choi, Ahchan Kim
In mobile SoC, clock sources such as PLLs, are expensive resources both in terms of area and power, and they are commonly shared by multiple clock consumers. To that end, the latest SoCs hold tens of PLLs and hundreds of
Samsung Electronics, Hwaseong, Korea
ISSCC 2022 Session 13 Digital Circuits
Deterministic Frequency Boost and Voltage Enhancements on the POWER10TM Processor
Brian T. Vanderpool1, Phillip J. Restle2, Eric J. Fluhr3, Gregory S. Still4,
Essex Junction, VT 1 2 Shrinking transistor sizes allow increased logic complexity in modern processors, but smaller dimensions increase power density and require reduced maximum voltage (VDDMAX) for reliability; this ca
Frank Campisano3, Ian Carmichael3, Eric Marz5, Rahul Batra3, Richard W
ISSCC 2022 Session 13 Digital Circuits
A 0.65V 1316µm2 Fully Synthesizable Digital Temperature Sensor Using Wire Metal Achieving 0.16nJ·%2-Accuracy FoM in 5nm FinFET CMOS
Junghyun Park, Jooseong Kim, Kwangho Kim, Jun-Hyeok Yang, Michael Choi, Jongshin Shin
performance of SoCs, which is rapidly increasing overall chip temperature. As a result, dynamic thermal management (DTM) using a number of temperature sensors is essential. For accurate temperature measurement, the senso
Samsung Electronics, Gyeonggi, Korea Recently, the number of hot spots
ISSCC 2022 Session 13 Digital Circuits
Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains
Chi-Hsiang Huang1, Arindam Mandal1, Diego Peña-Colaiocco1,
and wearable applications are aggressively duty-cycled to minimize leakage energy losses. Such systems operate predominantly in Sleep mode, regularly marked by brief intervals of Active operation to perform sensing or co
Edevaldo Pereira Da Silva2, Visvesh Sathe1 University of Washington, S
ISSCC 2022 Session 13 Digital Circuits
A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for
System Performance Scaling, Fast DVFS and Energy, Minimization
Xinjian Liu, Sumanth Kamineni, Jacob Breiholz, Benton H. Calhoun, Shuo Li University of Virginia, Charlottesville, VA A self-powered IoT system-on-chip (SoC) reduces power to sub-µW and employs multiple power-management
ISSCC 2022 Session 14 Wireless
A Monolithic GaN-Based Driver and GaN Power HEMT with Diode-Emulated GaN Technique for 50MHz Operation and Sub-0.2ns Deadtime Control
Yu-Yung Kao1, Tz-Wun Wang1, Sheng-Hsi Hung1, Yong-Hwa Wen1,
Taiwan 1 2 Monolithic gallium-nitride (GaN) high-electron-mobility transistors (HEMTs) have become popular due to their low parasitic capacitance, low on-resistance (RON), and no reverse recovery charge loss for high-fre
Tzu-Hsien Yang1, Si-Yi Li1, Ke-Horng Chen1, Ying-Hsi Lin2, Shian-Ru Li
ISSCC 2022 Session 14 Wireless
A 110V/230V 0.3W Offline Chip-Scale Power Supply with Integrated Active Zero-Crossing Buffer and Voltage-IntervalBased Dual-Mode Control
Christoph Rindfleisch, Bernhard Wicht
This paper presents an efficient and compact offline chip-scale power supply in 0.18µm high-voltage (HV) silicon-on-insulator (SOI) technology, suitable to supply IoT nodes, sensors, RF transceivers, LED strings, etc. fr
Leibniz University Hannover, Hannover, Germany
ISSCC 2022 Session 14 Wireless
A Monolithic GaN Direct 48V/1V AHB Switching Power IC with
Auto-Lock Auto-Break Level Shifting, Self-Bootstrapped
Hybrid Gate Driving, and On-Die Temperature Sensing Dong Yan, D. Brian Ma University of Texas at Dallas, Richardson, TX With 10-to-100-fold lower switching figure of merit (QGate$RON), GaN transistors present tremendous
ISSCC 2022 Session 14 Wireless
A 2.5−5MHz 87% Peak Efficiency 48V-to-1V Integrated Hybrid DC-DC Converter Adopting Ladder SC Network with CapacitorAssisted Dual-Inductor Filtering
Chen Chen, Jin Liu, Hoi Lee
With the rapid developments in big data analytics, non-isolated 48V-to-1V converters offer a competitive choice to support the increased power consumptions in CPUs and memories. For realizing a small output-to-input conv
University of Texas at Dallas, Richardson, TX
ISSCC 2022 Session 14 Wireless
2-Tx Digital Envelope-Tracking Supply Modulator Achieving 200MHz Channel Bandwidth and 93.6% Efficiency for 2G/3G/LTE/NR RF Power Amplifiers
Jun-Suk Bang*, Dongsu Kim*, Jeongkwang Lee, Sungyoub Jung,
Younghwan Choo, Seungchan Park, Young-Ho Jung, Jae-Young Ko, Takahiro Nomiyama, Jongbeom Baek, Jaeyeol Han, Sang-Han Lee, Ik-Hwan Kim, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho Samsung Electronics, Hwaseong, Korea *
ISSCC 2022 Session 14 Wireless
A 27W D2D Wireless Power Transfer System with Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS Control
Xiaofei Ma1,2, Yan Lu2, Wing-Hung Ki1
University of Macau, Macau, China 1 2 Compact and high-power bidirectional wireless power transfer (WPT) systems are desirable for mobile device-to-device (D2D) wireless fast charging. Prior WPT solutions [1-3] with inte
Hong Kong University of Science and Technology, Hong Kong, China
ISSCC 2022 Session 14 Wireless
A 1.2W 51%-Peak-Efficiency Isolated DC-DC Converter with a Cross-Coupled Shoot-Through-Free Class-D Oscillator Meeting the CISPR-32 Class-B EMI Standard
Dongfang Pan1, Guolong Li1, Fangting Miao1, Wei Sun1, Xiaohan Gong2,
interference (EMI) is essential for isolated DC-DC converters that are used in the harsh industrial environments. To pass the CISPR 32 Class-B EMI standard, a 4-layer PCB with a stitching capacitor implemented by the int
Lele Zhang2, Lin Cheng1 University of Science and Technology of China,
ISSCC 2022 Session 14 Wireless
A 68.3% Efficiency Reconfigurable 400-/800-mW Capacitive Isolated DC-DC Converter with Common-Mode Transient Immunity and Fast Dynamic Response by Through-PowerLink Hysteretic Control
Junyao Tang, Lei Zhao, Cheng Huang
Galvanically isolated voltage regulators (GIVRs) are widely used in industrial automation, electric vehicles, and medical devices to deliver power to low-voltage circuits across isolated domains and ensure human safety a
Iowa State University, Ames, IA
ISSCC 2022 Session 15 AI / ML
A Multi-Mode 8K-MAC HW-Utilization-Aware Neural Processing Unit with a Unified Multi-Precision Datapath in 4nm Flagship Mobile SoC
Jun-Seok Park1, Changsoo Park1, Suknam Kwon1, Hyeong-Seok Kim1,
Taeho Jeon1, Yesung Kang1, Heonsoo Lee1, Dongwoo Lee1, James Kim1, YoungJong Lee1, Sangkyu Park 1, Jun-Woo Jang2, SangHyuck Ha1, MinSeong Kim1, Jihoon Bang1, Suk Hwan Lim1, Inyup Kang1 Samsung Electronics, Hwaseong, Kore
ISSCC 2022 Session 15 AI / ML
A 65nm Systolic Neural CPU Processor for Combined Deep Learning and General-Purpose Computing with 95% PE
Utilization, High Data Locality and Enhanced End-to-End, Performance
network (DNN) accelerators, few works have targeted improving the end-to-end performance of deeplearning tasks, where inter-layer pre/post-processing, data alignment and data movement across memory and processing units o
Yuhao Ju, Jie Gu Northwestern University, Evanston, IL Despite recent
ISSCC 2022 Session 15 AI / ML
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning
Haozhe Zhu*1, Bo Jiao*1, Jinshan Zhang*1, Xinru Jia1, Yunzhengmao Wang1,
Tianchan Guan2, Shengcheng Wang2, Dimin Niu2, Hongzhong Zheng2, Chixiao Chen1, Mingyu Wang1, Lihua Zhang1, Xiaoyang Zeng1, Qi Liu1, Yuan Xie2, Ming Liu1 Fudan University, Shanghai, China Alibaba DAMO Academy, Shanghai, C
ISSCC 2022 Session 15 Digital Processors
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet
Kazutoshi Hirose*, Jaehoon Yu*, Kota Ando, Yasuyuki Okoshi,
Ángel López García-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura Tokyo Institute of Technology, Yokohama, Japan *Equally Credited Authors (ECAs) Since the advent of the Lottery Ticket Hypothes
ISSCC 2022 Session 15 AI / ML
A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration
Fengbin Tu1,2, Yiqi Wang1, Zihan Wu1, Ling Liang2, Yufei Ding2, Bongjin Kim2,
have been proposed for edge deep learning (DL) acceleration. They usually rely on analog CIM techniques to achieve highefficiency NN inference with low-precision INT multiply-accumulation (MAC) support
Leibo Liu1, Shaojun Wei1, Yuan Xie2, Shouyi Yin1 Tsinghua University,
ISSCC 2022 Session 15 AI / ML
DIANA: An End-to-End Energy-Efficient DIgital and ANAlog Hybrid Neural Network SoC
Kodai Ueyoshi*1, Ioannis A. Papistas*2, Pouya Houshmand1,
Giuseppe M. Sarda1,2, Vikram Jain1, Man Shi1, Qilin Zheng1, Sebastian Giraldo1, Peter Vrancx2, Jonas Doevenspeck2, Debjyoti Bhattacharjee2, Stefan Cosemans2, Arindam Mallik2, Peter Debacker2, Diederik Verkest2, Marian Ve
ISSCC 2022 Session 15 AI / ML
ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory
Jin-O Seo1, Mingoo Seok2, SeongHwan Cho1
One of the notable trends in convolutional neural network (CNN) processor architecture is to embrace analog hardware to improve energy efficiency in performing multiply-andaccumulate (MAC). Prior works investigated charg
KAIST, Daejeon, Korea; 2Columbia University, New York, NY
ISSCC 2022 Session 15 Digital Processors
Analog Matrix Processor for Edge AI Real-Time Video Analytics
Laura Fick1, Skylar Skrzyniarz1, Malav Parikh1, Michael B. Henry2, David Fick1
Mythic, Austin, TX Mythic, Redwood City, CA 1 2 One of the!salient!hurdles for wide adoption of!machine learning!(ML)!has been!efficient and high-performance!edge compute.!ML developers!use very large, expensive, and pow
ISSCC 2022 Session 15 AI / ML
A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification
Tzu-Hsiang Hsu*, Guan-Cheng Chen*, Yi-Ren Chen, Chung-Chuan Lo,
artificial intelligence (AI) for applications requiring image classification are in growing demand. However, the imager plus dedicated AI accelerator solution [1] suffers from the burdens of power and latency caused by t
Ren-Shuo Liu, Meng-Fan Chang, Kea-Tiong Tang, Chih-Cheng Hsieh Nationa
ISSCC 2022 Session 16 AI / ML
DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware
Dewei Wang1, Chuan-Tung Lin1, Gregory K. Chen2, Phil Knag2,
Ram K. Krishnamurthy2, Mingoo Seok1 Columbia University, New York, NY Intel, Portland, OR 1 2 In-memory-computing (IMC) SRAM architecture has gained significant attention as it achieves high energy efficiency for computi
ISSCC 2022 Session 16 AI / ML
A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2 RRAM Binary/Compute-in-Memory Macro with 4.23× Improvement in Density and >75% Use of Sensing Dynamic Range
Samuel D. Spetalnick1, Muya Chang1, Brian Crafton1, Win-San Khwa2,
Compute-in-Memory (CIM) using emerging nonvolatile (eNVM) memory technologies, such as resistive random-access memory (RRAM), has been shown by several implemented macros to be an energy-efficient alternative to traditio
Yu-Der Chih3, Meng-Fan Chang2, Arijit Raychowdhury1 Georgia Institute
ISSCC 2022 Session 16 Digital Circuits
A 40nm 60.64TOPS/W ECC-Capable Compute-inMemory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems the sum-of-product error and correct the CIM error. As a result, we pay the penalty of serializing the read operation temporarily. (4) We localize the BL where the sum-ofproduct error has occurred by comparing the CIM result and the correct serial result.
(5) Lastly, victim BLs are tracked with a status register and regularly refreshed to combat, resistance drift and variat
Muya Chang1, Samuel D. Spetalnick1, Brian Crafton1, Win-San Khwa2, Yu-Der Chih3, Meng-Fan Chang2, Arijit Raychowdhury1 In Fig. 16.3.4, we illustrate physical design considerations, power plan, software programmability, a
ISSCC 2022 Session 16 Digital Circuits
Flex6502: A Flexible 8b Microprocessor in 0.8µm MetalOxide Thin-Film Transistor Technology Implemented with a Complete Digital Design Flow Running Complex Assembly Code
Hikmet Çeliker1,2, Antony Sou3, Brian Cobb3, Wim Dehaene1,2, Kris Myny1,2
PragmatIC Semiconductor, Cambridge, United Kingdom 1 3 Integrated circuits based on thin-film transistors (TFTs) are attractive for use in many areas, including the Internet-of-Things (IoT), where ultra-thin circuits on
imec, Leuven, Belgium; 2KU Leuven ESAT, Leuven, Belgium
ISSCC 2022 Session 16 Digital Circuits
FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems
Yuqi Su1, Tony Tae-Hyoung Kim1, Bongjin Kim2
University of California, Santa Barbara, CA 1 2 cycle of operation, the stored spin value is distributed to the four directions based on the lattice graph hardware topology. Note that a spin input can be bypassed to the
Nanyang Technological University, Singapore, Singapore
ISSCC 2022 Session 16 Digital Circuits
A 65nm 63.3µW 15Mbps Transceiver with SwitchedCapacitor Adiabatic Signaling and Combinatorial-PulsePosition Modulation for Body-Worn Video-Sensing AR Nodes
Baibhab Chatterjee, Arunashish Datta, Mayukh Nath, Gaurav Kumar K,
virtual reality (VR) demands 1) high speed (>10Mbps) data transfer among wearable devices around the human body with 2) low transceiver (TRX) power consumption for longer lifetime, especially as communication energy/b is
Nirmoy Modak, Shreyas Sen Purdue University, West Lafayette, IN Recent