DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware

📋 论文概要

该论文提出了一种基于近似算术硬件的全数字内存计算宏（DIMC），用于解决传统模拟混合信号内存计算易受工艺、电压、温度变化影响的问题。在28nm工艺下实现了2219TOPS/W的能效和2569F2/b的面积效率，显著提升了卷积神经网络的推理精度和可靠性。

💡 主要创新点

• 首次提出基于近似算术硬件的全数字内存计算架构，避免了模拟电路对PVT变化的敏感性，提升了计算精度。
• 设计了高能效的数字计算单元，在28nm工艺下实现了2219TOPS/W的能效和2569F2/b的面积效率，优于同期模拟混合信号方案。

🏷 关键词

📄 原文摘要

Ram K. Krishnamurthy2, Mingoo Seok1 Columbia University, New York, NY Intel, Portland, OR 1 2 In-memory-computing (IMC) SRAM architecture has gained significant attention as it achieves high energy efficiency for computing a convolutional neural network (CNN) model [1]. Recent works investigated the use of analog-mixed-signal (AMS) hardware for high area and energy efficiency [2, 3]. However, AMS hardware output is well known to be susceptible to process, voltage, and temperature (PVT) variations, limiting the computing precision and ultimately the inference accuracy of a CNN. We reconfirmed, through the simulation of a capacitor-based IMC SRAM macro that computes a 256D binary dot product, that the AMS computing hardware has a significant root-mean-square error (RMSE) of 22.5% across the worst-case voltage, temperature (Fig. 16.1.1 top left) and 3-sigma process variations (Fig. 16.1.1 top right). On the other hand, we can

👥 作者与机构

Dewei Wang1, Chuan-Tung Lin1, Gregory K. Chen2, Phil Knag2,