AI / ML

Harrie A. C. Tilmans, Anabel De Proft, Barundeb Dutta, Carolina Mora Lopez imec, Heverlee, Belgium *Equally Credited Authors (ECAs) Abstract We present a waveguide-based optogenetics neural probe with 1,280 electrodes, 3

Abstract We propose a light-adaptive retinal prosthesis (LARP) SoC, which employs power-aware light adaptation achieving a wide light-sensing DR of 55.48dB. Pixel clustering enables a compact pixel size of 80×80μm2, enha

Abstract This work presents a hybrid optogenetic stimulation system with sub-threshold electrical stimuli that lower the optical threshold and reduce energy consumption. It achieves 90.75% LED driving efficiency through

Chinese Academy of Sciences, Beijing, China, 4Soochow University, Suzhou, China *Equally Credited Authors (ECAs) 1 3 Abstract This 1024-electrode neural interface solves the power, area, and bandwidth bottleneck by combi

Abstract To enable high-fidelity wearable ExG acquisition, this paper presents an NS-SAR ADC that performs 2nd-order shaping of both quantization and kT/C noises through a multi-tasking integrator (MTI) and loop dynamics

Shijiazhuang, China National Tsing Hua University, Hsinchu, Taiwan *Equally Credited Authors (ECAs) 1 4 Abstract This paper reports an olfactory processor with on-chip transfer learning for cross-hospital and cross-pulmo

Abstract We present a patient-independent, prototype-based spatio-temporal CNN processor for seizure detection, achieving high accuracy without patient-specific data, at an energy of 16.4nJ/class and latency of <120ms. A

*Equally Credited Authors (ECAs) 1 Abstract This work presents a 65nm ExG SoC for smart glasses, enabling low-power neural interaction. A 10-ch AFE and on-chip CNN deliver real-time EOG/EMG/EEG inference. Ondevice contin

Abstract This paper presents a fast impedance-measurement IC for large-scale piezo-resistive sensor arrays. It features a unified differential time-to-digital demodulation architecture that reads out impedance directly t

*Equally Credited Authors (ECAs) 1 Abstract This paper presents a frame-rate-scalable duty-cycled electrical impedance tomography system to reduce average power consumption. A proposed multiple-input multiple-output curr

Abstract This work presents ReFIND, an SoC integrating together 16 resolution-reconfigurable AFEs, a feature extractor, and a classifier. The VCO ADC architecture trades power for resolution by scaling the integration ti

Abstract LLMs face decoding bottlenecks. Speculative Decoding (SD) reduces latency via a small draft model for serial decoding and a large target model to verify in parallel. Despite this advantage, it still suffers from

Abstract This paper presents Tri-Oracle, a VLM accelerator exploiting token, attention, and weight redundancies. A Token Merging Unit (TMU) merges 68% of redundant tokens. An Attention Head Prediction Unit (AHPU) predict

Abstract This work presents SoulMate, a fully on-device mobile intelligence system-on-chip, integrating retrieval-augmented generation (RAG) and fine tuning of a personal LLM. SoulMate is fabricated in 28nm CMOS with a n

Sciences, Beijing, China, 3Zhangjiang Laboratory, Shanghai, China Xi’an UniIC Semiconductors, Xi’an, China 1 4 Abstract A high-bandwidth-density (12.77GB/s/mm2) high-memory-density (99.4Mb/mm2) lowenergy-consumption (0.6

2University of Chinese Academy of Sciences, Beijing, China Columbia University, New York, NY *Equally Credited Authors (ECAs) 1 3 Abstract Previous near-memory computing (NMC) or in-memory-computing (IMC) NANDs suffers f

Yao-Kai Yeh1, De-Qi You1, Ashwin Sanjay Lele3, Brian Crafton3, Bo Zhang3, Ping-Sheng Wu2, Ya-Tang Yang1, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Meng-Fan Chang1,2 National Tsing Hua University

Abstract This paper proposes a bit-parallel digital CIM macro featuring a lossless compressor based on transition-counting-lines (TCLs) for bit-column addition. The bus TCL incorporates signbit extension to support signe

Jen-Chun Tien1, De-Qi You1, Ping-Sheng Wu2, Bo Zhang3, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Meng-Fan Chang1,2 National Tsing Hua University, Hsinchu, Taiwan, 2TSMC Corporate Research, Hsinchu, Taiwan, 3TSMC

2University of Chinese Academy of Sciences, Beijing, China Columbia University, New York, NY *Equally Credited Authors (ECAs) 1 3 Abstract Previous non-volatile CIM (nvCIM) macros suffer from low storage density, unneces

China, 3Xiaomi, Beijing, China, 4Peking University, Beijing, China 1 Abstract Conventional FP-CIMs suffer from fixed preserved bit-width (PBW), limiting their adaptability and efficiency. This work proposes the first MXF

Abstract A 17.9-to-22.4GHz quad-core inverse-Class-F VCO achieving PN of −145.6 to −141dBc/Hz and an FoM of 194.3 to 196.9dBc/Hz is reported. The VCO features a circular pentafilar transformer tank that provides high Q1/

controller to overcome the interference issue between touch and display electrodes. In addition, an analog frontend (AFE) circuit is introduced to suppress coupling noise from display, and a dedicated neural network engi

Abstract This paper presents a compact 26/38GHz reconfigurable dual-band low-noise amplifier (LNA) for a narrow-LO dual-side mixing. By adopting a transformer-based pole-zeroinversion image-rejection technique, the LNA a

Abstract A 16nm FinFET transformer-based diffusion model processor chip is fabricated for supporting class-conditional DiT-XL/2 and text-to-image PixArt-α with 98ms and 134ms generation time per step with 7.37TOPS and 14

Abstract This work presents an AI-RAN channel estimation accelerator for next-generation communications, offering hyper reliability, low latency, and universal frequency range coverage, thereby meeting B5G/6G requirement

Abstract This work presents a bidirectional 5kV-isolated DC-DC converter, fully-integrated in a 180nm SOI CMOS process. The design uses a distributed multi-winding transformer to maximize utilization of the standard on-c

*Equally Credited Authors (ECAs) 1 Abstract This paper presents a single-transformer multi-output isolated DC-DC converter generating three regulated rails (+15V, −5V, and +5V) from wide 12/24V inputs. By sharing a commo

Switzerland, 5SynSense, Ningbo, China 1 4 Abstract SpikeRAM is a high efficiency (48.1pW/Synapse/Bit) memory-centric neuromorphic system with perception, computing and on-chip learning, achieving 464M synapses and 8.28mW

*Equally Credited Authors (ECAs) Abstract This paper presents a DCIM-based accelerator for on-device streaming multi-speaker ASR (MS-ASR), featuring: 1) a context-aware redundancy skipping scheme with online sparse block

Abstract A MIMO RF harvester in the 5G 28-GHz band with spatial MPPT is introduced to self-align high-gain harvesting direction with maximum power availability. Spatial scanning is enabled by a hybrid 2-level RF/DC anten

Abstract This work presents a 28nm CMOS SR-VCO enabled by a dual-mode transformer with magnetic control, achieving a wide tuning range of 10.2 to 16.2GHz (45.2%) and a high FoMT/FoMAT@10MHz of 201.1/207.7dBc/Hz. A transf

Abstract We present a 55nm mixed-signal K-SAT solver with parallel-variable update algorithm for improved convergence and a compute-in-memory fabric that maps arbitrary-order K-SAT instances without preprocessing. It sol

Yuju Cho1, Rex Che-Yuan Liu1, Ericbill Wang1, You-Ming Tsao1, Hugh Mair2, Shih-Arn Hwang1 MediaTek, Hsinchu, Taiwan MediaTek, Austin, TX 1 2 For flagship smartphones, the gaming experience has become one of essential dem

Initially applied for image synthesis [1], Diffusion Models (DMs) have been rapidly expanded into many content-generation tasks, e.g. 3D scenes [2-3] or video [4], and deliver exceptional performance. Figure 37.6.1 provi

Hyungwoo Lee1, Wooseok Yi1, Seungchul Jung1, Daekun Yoon1, Shinhee Han3, Saeyoon Chung3, Kilho Lee3, Jeong-Heon Park3, Kangho Lee3, Sang Joon Kim1, Donhee Ham1,4 Samsung Advanced Institute of Technology, Suwon, Korea Seo

Hefei CLT Microelectronics, Hefei, China 1 2 Integrated isolated DC-DC converters, using either on-chip [1-4] or package transformers [5-7], have been developed to minimize size and cost while achieving isolation ratings

Luhong Liang2, Yitong Zhou2, Di Pang2, Man-To Yung2, Dong Zhang1,2, Xijie Huang1,2, Shih-Yang Liu1,2, Yongkun Wu1,2, Fengshi Tian1,2, Chi-Ying Tsui1,2, Fengbin Tu1,2, Kwang-Ting Cheng1,2 The Hong Kong University of Scien

revolutionized a wide range of AI applications, which motivates a surge in research to develop energy-efficient hardware accelerators. Most prior efforts have concentrated on enhancing on-chip computational energy effici

Kai-Feng Chang1, Yu-Ching Su1, Tsung-Han Hsieh1, Yu-Kuan Jian1, Wen-Ching Chen2, Nian-Shyang Chang2, Chun-Pin Lin2, Chi-Shi Chen2, Chao-Tsung Huang1 National Tsing Hua University, Hsinchu, Taiwan Taiwan Semiconductor Res

Mookyung Kang, Heeseok Lee, Jinwon Kang, Taeho Jeon, Dongwoo Lee, Yesung Kang, Kyungmok Kum, Geunwon Lee, Hongki Lee, Minkyu Kim, Suknam Kwon, Sung-beom Park, Dongkeun Kim, Chulmin Jo, HyukJun Chung, Ilryoung Kim , Jongy

Byeongwook Bae1, Yojung Cha1, Wooyoung Choe1, Jonguk Choi1, Younggeun Choi1, Ki Jin Han2, Seokha Hwang1, Kiseok Jang1, Jaewoo Jeon1, Hyunmin Jeong1, Yeonsu Jung1, Hyewon Kim1, Sewon Kim1, Suhyung Kim1, Won Kim1, Yongseun

crucial in delivering vital information for medical diagnostics and research applications. Recently, the demand for biopotential recording using two electrodes has grown thanks to its better user experience and lower cos

University of Pittsburgh, Pittsburgh, PA In addition, the first-stage amplifier bandwidth is set slightly below the Nyquist rate (100kHz), preventing aliasing of thermal noise and input interference. Therefore, the input

Yu Huang1, Junyu Ma1, Chae Lim1, Lingyun Xu1, Shucheng Gong1, Weian Deng1, Qiaosong Deng1, Jin Che1, Sudip Nag1, Joshua Olorocisimo1, Rhianna Singh1, Yanze Wang1, Jose Sales Filho1, Mandana Mohaved2, Homeira Moradi2, Geo

Swarnava Ghosh1, Eric Liu1, Naize Yang1, Junyu Ma1, Hanfeng Cai1, Laura Kondrataviciute1,2, Qiaosong Deng1, Suneil K. Kalia1,2, Andrew G. Richardson3, Ping-Hsuan Hsieh4, Roman Genov1, Xilin Liu1 University of Toronto, To

for preventing Sudden Cardiac Death (SCD) by identifying life-threatening heart rhythms, such as ventricular tachycardia (VT) and ventricular fibrillation (VF) [1], and enabling timely intervention via implantable cardio

Next-generation brain-computer interfaces will enable motor and speech decoding in humans [1-3] and improve our understanding of brain function [4]. To achieve this requires high-density multi-electrode arrays (HD-MEA) [

Brain-machine interfaces (BMIs) are a promising technology that can be applied to AR/VR interfaces, neural prostheses, and machine control. Figure 15.1.1 shows BMI systems based on the source of decoded neural activities

Yuhui Shi, Lizheng Ren, Yibo Mai, Feiran Liu, Jinwu Chen, Zhaoyang Zhang, An Guo, Tianzhu Xiong, Bo Wang, Xinning Liu, Weiwei Shan, Bo Liu, Hao Cai, Jun Yang, Xin Si Southeast University, Nanjing, China Hybrid-domain CIM