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ISSCC 2026Session 19 · HIGH-VOLTAGE, ISOLATED AND DISPLAY POWERAI / ML180nm SOI CMOS

A Fully Integrated Bidirectional 5-Level Isolated DC-DC Converter with 42.5% Efficiency and 170mW/mm2 Transformer Power Density

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📋 论文概要

本文提出一种全集成双向5kV隔离DC-DC转换器,采用180nm SOI CMOS工艺和分布式多绕组变压器,通过5电平混合全桥功率级实现波形整形与电流均衡,达到42.5%峰值效率和170mW/mm2变压器功率密度。

💡 主要创新点

核心指标
42.5% peak efficiency, 170mW/mm2 transformer power density, 69mW/mm2 system power density
工艺节点
180nm SOI CMOS
重要性
发表年份
ISSCC 2026

🏷 关键词

隔离DC-DC转换器全集成5电平多绕组变压器SOI CMOS

📄 原文摘要

Abstract This work presents a bidirectional 5kV-isolated DC-DC converter, fully-integrated in a 180nm SOI CMOS process. The design uses a distributed multi-winding transformer to maximize utilization of the standard on-chip metal stackup. A 5-level hybrid full-bridge power stage allows fundamental and harmonic waveform shaping with current ballasting. The design achieves peak efficiency of 42.5% at over 550mW, for system power density over 69mW/mm2 and transformer power density over 170mW/mm2. Power transfer across a galvanic isolation barrier is critical for safety and reliability in applications such as biomedical implants and isolated gate drivers [1,2]. The key challenges in this area are to achieve high power density with galvanic isolation over 5kV while maximizing power-transfer efficiency. Figure 19.8.1 shows past solutions which use separate transmitter (TX) and receiver (RX) chips and typically a transformer (XFMR)

👥 作者与机构

Kishalay Datta, Yue Wu, Charles Sullivan, Jason Stauth

Dartmouth College, Hanover, NH

分类:AI / ML · 年份:ISSCC 2026