2026

AI is redefining the semiconductor landscape. Exponential growth in compute, bandwidth, and power efficiency is driving the proliferation of agentic and physical AI. The paradigm is shifting from performance alone to bre

Quantum computing is advancing rapidly, offering the potential to transform computational paradigms and tackle problems that are intractable for classical systems. Realizing practical quantum systems demands the developm

Cadence, San Jose, CA Abstract The AI supercycle is rapidly increasing demand for compute performance and scalability across all levels, from data centers to edge devices. By 2030, the semiconductor total addressable mar

Abstract Developing custom chips for specific applications enables fundamentally better products. As part of a full-stack optimization approach to product design, application-specific systems-on-chips (SoCs) have been on

Paris, France 1 Abstract This paper presents a 3nm SoC, designed for software defined vehicles, integrating various functions for zone-based computing. The chip includes a 1,080kDMIPS APU, 400TOPS NPU and 51.2GB/s inter-

Abstract We present a 55nm mixed-signal K-SAT solver with parallel-variable update algorithm for improved convergence and a compute-in-memory fabric that maps arbitrary-order K-SAT instances without preprocessing. It sol

Huaichung Chang1, C.-J. Tsai1, Yi-Chang Zhuang1, Barry Chen1, Ericbill Wang1, Hugh Mair2, Shih-Arn Hwang1 MediaTek, Hsinchu, Taiwan, 2MediaTek, Austin, TX 1 Abstract This work presents dynamic mobile-performance augmenta

Abstract A 2nm clock-edge architecture (CEA) for an NPU matrix-multiplication unit (MXU) features dual-edge-triggered (DET) flip-flops, DET clock-gating circuits, and an adaptive clock dutycycle controller to achieve iso

Abstract An all-digital high-performance standalone fractional divider (FDIV) is presented. It leverages a robust replica-free least-mean square (LMS)-based digital-to-time converter (DTC) background calibration using a

IBM T. J. Watson Research Center, Yorktown Heights, NY 1 5 Abstract A 28nm SoC solution with integrated proactive power management for droop mitigation is demonstrated combining a neural droop management unit, integrated

Carlos Tokunaga1, Ram K. Krishnamurthy1, James W. Tschanz1 Intel, Hillsboro, OR, 2Intel, Austin, TX, 3Intel, Santa Clara, CA 1 Abstract A manycore DNN processor leverages hybrid bonding in a 14×4×2 mesh network on chip t

Abstract The K-SAT problem is NP-complete and costly on von Neumann machines. Several ASIC solvers have been proposed to mitigate this, but they rely on inefficient crossbar mapping, overlook community structures and lac

Abstract We present a 65nm digital Ising chip with an advanced column-bipartite topology, featuring densely connected spins with a degree of 56 and 8b coefficients for mapping and solving computationally intensive combin

Abstract We present SharpSAT, a heuristic-learning SAT accelerator that achieves fast solution times of 0.8$s for SAT and 16.1$s for UNSAT cases. Our design integrates: a fast clause learning unit that prunes the search

Abstract This paper presents a 14b 400MS/s Pipelined-SAR ADC utilizing a front-end TDC with a linearized rail-to-rail input VTC. A background calibration engine corrects VTC gain and timedomain offset errors by monitorin

receivers achieves -95dBc THD and 103dB SFDR in 270MHz bandwidth, exceeding state-of-the-art by >20dB. Wideband high spectral purity is realized with a highly linear all-pass filter, high- SFDR coarse ADCs, a fast tone-b

(ECAs) 1 Abstract This paper presents a 28nm CMOS 500MS/s 12b three-stage pipeline SAR ADC based on a triple-cascode single-stage floating residue amplifier with virtual supply extension to improve its efficiency and lin

Abstract This work proposes a pipelined-SAR ADC featuring a current-buffer-based integrating sampler that presents a resistive input with good linearity. A floating charge transferrer (FCT) with multi-bit pre-conversion

conversion. Samplers with switched buffers are proposed to realize wideband sampling in rank 1 driven by a multi-phase clock generated by a delay line with feedforward coupling. Making the slope nonlinear compensates sta

Satoshi Yoshizawa, Atsuya Suzuki, Soichi Kato, Takahiro Naito, Keigo Bunsen, Tomohiro Matsumoto, Yasushi Katayama Sony Semiconductor Solutions, Atsugi, Japan Abstract A 2.6mW, 1GHz, 42dB-SNDR sub-ADC is presented. A hybr

Chen-Kai Hsu1, Zhao Li6, Janet Brunsilius4, Enrique Alvarez-Fontecilla4, Robert Bishop1, Paul Wilkins1, Hassan L’Bahy1, Adalberto Cantoni1, Nuo Zhang1, Kaung Myat San Oo1, Cihan Asci1 Analog Devices, Wilmington, MA, 2Ana

RF-sampling DAC. By introducing a switch driver with process-and-temperature-adaptive (PT-adaptive) level shifting and enhanced low-crosspoint control, the DAC demonstrates an IMD3 of 70.8dBc at 7.2GHz and 16Gs/s, and a

variable-slope digital-to-time converter (DTC) is presented. Supply insensitivity is achieved by a background calibration loop, without affecting DTC linearity or noise. Measured results demonstrate 65.6fs jitter upon 6.

inverse-constant-slope DTC for rejection of supply disturbances is presented. Compared to traditional fractional-N digital PLLs, it requires no additional calibration for supply rejection or additional supply-insensitive

Abstract A 14GHz chopper-refolding sampling PLL is implemented in 28nm CMOS, integrating a kT/C-noise-cancellation sampling phase detector (SPD) and a self-injection VCO with harmonic-impedance expansion. The SPD decoupl

Abstract This paper presents a 0.65-to-1V, 10.5-to-11.85GHz wide-VDD-range (WV) fractional-N sampling PLL. The QE-reduction WV SPD, high-linearity 2-stage DTC, and DCC-aided QE dithering method are proposed to address th

Abstract Pure microwave sources are vital for precision instrumentation, but conventional schemes are bulky and costly. CMOS oscillators are inexpensive and compact yet limited by phasenoise performance. To address this,

Abstract This work presents a 28nm deeply power-scalable reconfigurable series-resonance/ClassF VCO with mutual-inductance self-cancellation and hybrid 8-shaped coupling techniques, achieving power scalability from 5.7 t

Abstract This work presents a 28nm CMOS SR-VCO enabled by a dual-mode transformer with magnetic control, achieving a wide tuning range of 10.2 to 16.2GHz (45.2%) and a high FoMT/FoMAT@10MHz of 201.1/207.7dBc/Hz. A transf

China, 4China Mobile Research Institute, Beijing, China, Xiamen Industrial Technology Research Institute, Fujian, China, 6Bytedance China, Beijing, China, 7Huawei Technologies, Shenzhen, China 1 5 Abstract We present the

*Equally Credited Authors (ECAs) 1 Abstract This paper introduces a unified algorithmic design flow for low-noise amplifiers (LNAs), spanning specifications to layout and integrating topology, architecture, circuit, and

Abstract A quantum-inspired analog variable k-SAT solver supporting up to 200 variables and 1016 clauses. Enabling techniques include make/break feedback, distributed k-SAT logic, digital macro coupling, and feedback opt

Abstract A 0.8-to-2.6GHz N-path filter with gm-boosted HBT switches and inverse-designed nonresonant passive networks is presented to enhance dynamic range and tunability of passively coupled higher-order N-path filters.

Abstract An algorithmic topology optimization framework is presented to autonomously synthesize nonintuitive, multilayered wideband mm-Wave LNAs with arbitrary stage count. Cooptimization of actives and passives directly

Abstract A through-silicon interconnect module for 3D integration utilizing THz coupling is presented, which achieves a record high data rate of 264Gb/s and efficiency of 0.33pJ/b. Both bidirectional point-to-point link

Abstract This paper presents an ultra-energy-efficient MRM based 8-channel optical WDM NRZ transmitter, employing a scalable driver topology combined with monolithic electronic– photonic integration, which minimizes pack

Abstract A laser diode driver with supply-intrinsic current shaping for FMCW LiDAR is presented. By combining a fast optical loop and an efficient switching loop, and with the LD fitted model realized in analog circuits,

Abstract This paper presents a 40Gb/s 1-to-N VCSEL driver using 150nm GaN HEMT with fT/fMAX of 50GHz/154GHz. The proposed topology can drive VCSEL arrays in series or parallel without the need of pre-driver, using a comm

Abstract A sticker-like light sensing system is demonstrated in flexible N type-only IGZO TFT. It reuses RF signals for harvested battery charging and backscattered communications, and repurposes resistors as light senso

Abstract We present a CMOS self-programmable twin PUF which can be formed at the pre-waferdicing stage via photovoltaic harvesting. Two adjacent PUFs share entropy during oxide breakdown, enabling mutual authentication w

Kazuki Yamauchi2, Indra K V1, Masahiro Kano2, Sirisha Bhamidipati1, Sneha Bhatia1, Seema Malhotra1, Naoki Ojima2, Ella Wu3, Zhiyong Yang3, Frank W. Tsai3, Mathias Bayle2, Naoyuki Minami2, Yasuyuki Fujihara2, Kei Kitamura

Sang-Hoon Jung, Seunghan Woo, Donggeon Kim, Jonghyuk Kim, In Jung, Junsoo Kim, Jae-Joon Song, InCheol Nam, Young-Hun Seo, Sungsoo Yim, Jemin Park, Changsik Yoo, SangJoon Hwang Samsung Electronics, Hwaseong, Korea Abstrac

Abstract This work presents a single-rail, 21.04Mb/mm2 logic-bitcell 2-port SRAM in a 2nm nanosheet technology for CPU, GPU and NPU caches. The implemented xBIT cell in a 2R×1C configuration uses dual BL for balanced NMO

Seungpil Ko2, Jaechul Shim2, Shinhee Han1, Kiseok Suh1, Sohee Hwang1, Hyunchang Lee1, Jonghoon Jung1, Sanghoon Baek1 Samsung Semiconductor, Gyunggido Kiheung, Korea, 2Samsung Semiconductor, Gyunggido Hwasung, Korea 1 Abs

Chao-Jung Hung1, Tan-Li Chou1, Chih-Hui Weng2, Chia-Yu Wang2, J.J. Wu2, Harry Chuang2, Yih Wang1, Yu-Der Chih1, Tsung-Yung Jonathan Chang1 TSMC Design Technology, Hsinchu, Taiwan, 2TSMC, Hsinchu, Taiwan 1 Abstract A 16nm

Abstract This paper presents a TCAM design that includes a bank-less small-grain TCAM-macro compiler, a configurable soft-macro generator, selective macro-wise pipelined search techniques, and a split data-bus architectu

ChangHyun Bae, Joohwan Kim, Je-Min Ryu, Shin-haeng Kang, Jaehoon Lee, Young-Uk Chang, JaeKyung Lee, JongTae Hwang, Daehwan Seo, Ki-Heon Na, Young Guen Song, Daihyun Lim, Kyung-Soo Ha, Young-Soo Sohn, Sang-Joon Hwang Sams

JongMoon Choi, Sung-Woo Yoon, Sang Yun Kim, Dongkeon Lee, Minsoo Jang, Daehyun Kwon, Sangyong Lee, Jinguk Kim, Jonghyuk Kim, In Jung, Taeha Song, Chang Won Kim, Seung Ho Baek, Jinyong Choi, Young-Hun Seo, Won Ho Choi, Ch

Abstract This work presents a PV energy harvesting interface using a self-clamp CSCR SC converter. It reduces VCF stress without additional SC stages, enabling low-voltage CFs, 17.1mW/mm2 power density and 90% peak PCE.

Abstract A MIMO RF harvester in the 5G 28-GHz band with spatial MPPT is introduced to self-align high-gain harvesting direction with maximum power availability. Spatial scanning is enabled by a hybrid 2-level RF/DC anten