A 72Gb/s/pin Single-Ended Driver-Cooperative Coded PAM3 Transceiver with Asymmetric Data-Dependent Equalization and Bias-Peaking for Chiplets and Memory Interfaces

📋 论文概要

本文提出了一种在28nm CMOS工艺中实现的72Gb/s/pin单端PAM-3收发器。通过驱动协同编码降低了≥46%的信令功耗，并采用非对称数据依赖均衡和偏置峰值技术，将眼图面积扩大1.9倍和2.8倍，从而解决了PAM-3不同边沿ISI和开关抖动问题。

💡 主要创新点

• 提出驱动协同编码（Driver-Cooperative Coding）以增强信号完整性并降低信令功耗≥46%。
• 采用非对称数据依赖均衡和偏置峰值（Asymmetric Data-Dependent Equalization and Bias Peaking）减轻PAM-3不同边沿ISI和开关抖动，眼图面积扩大1.9倍和2.8倍。
• 实现1/8速率前向时钟乘法方案（Forwarded-Clock Multiplication）以支持低功耗和宽范围去偏移。

🏷 关键词

📄 原文摘要

Abstract This paper presents a 72Gb/s/pin PAM-3 single-ended transceiver in 28nm CMOS. Drivercooperative coding enhances signal integrity and reduces signaling power by ≥46%. Asymmetric data-dependent equalization and bias peaking mitigate PAM-3 different edge ISI and switching jitter, enlarging eye area by 1.9# and 2.8#. A 1/8-rate forwarded-clock multiplication scheme enables low-power and wide-range de-skew. The transceiver supports a 72Gb/s/pin data rate, with power efficiencies of 0.7pJ/b at 48Gb/s and 1.17pJ/b at 72Gb/s. The rapid growth of AI and cloud-computing applications drives demand for high-speed and low-power single-ended (SE) interfaces for chiplets and memories [1-6]. To increase SE interface data rates, PAM3 signaling is emerging as a promising candidate [1-3]: offering a 1.5× bandwidth efficiency over NRZ and better noise and crosstalk immunity than PAM4. However, compared to NRZ, PAM3’s higher ISI sensitivity and switching-jitter (SWJ)

👥 作者与机构

Hongzhi Wu, Xuxu Cheng, Yangyi Zhang, Xiongshi Luo, Zhenghao Li, Weitao Wu, Quan Pan

Southern University of Science and Technology, Shenzhen, China