A 200MP 0.61μm-Pixel-Pitch CMOS Imager with Sub-1e- Readout Noise Using Interlaced-Shared Transistor Architecture and On-Chip Motion Artifact-Free HDR Synthesis for 8K Video Applications

📋 论文概要

这篇论文提出了一款200MP、0.61μm像素间距的CMOS图像传感器，采用交错共享晶体管架构实现了亚1e-读出噪声（0.7e-），并具备片上无运动伪影的高动态范围合成与DCG比例自校准算法，支持8K HDR视频的高速读出。主要解决了超高像素密度下的低噪声读出和高动态范围成像难题。

💡 主要创新点

• 采用交错共享像素架构（Interlaced-Shared Transistor Architecture），在0.61μm像素间距下实现0.7e-的极低读出噪声
• 片上无运动伪影的高动态范围合成技术，单帧动态范围达到77dB
• 提出DCG比例自校准算法，解决了转换增益比非均匀性问题
• 基于22nm工艺的高速读出电路设计，兼顾低功耗与高性能，支持8K HDR视频

🏷 关键词

📄 原文摘要

Abstract We propose a 200MP 0.61µm pixel size CMOS image sensor featuring: 1) an interlacedshared pixel architecture to achieve a 0.7e- readout noise, 2) an on-chip motion artifact-free HDR synthesis with single-frame dynamic range of 77dB, 3) a DCG ratio self-calibration algorithm to address the CG ratio non-uniformity, and 4) a 22nm high-speed readout circuit suitable for 8K HDR video with an optimal balance of low-power and high-speed performance. The resolution race is once again gaining momentum. Driven by advancements in pixel technology and ongoing developments in CMOS processes, the demand for higher resolutions, reaching up to 200 megapixels (MP), is increasingly prominent in the latest high-end smartphones [1]. To accommodate the constraints of lens modules and device compartments, the pixel pitch for 200MP sensors typically falls within the sub-0.7 µm range. One of the leading designs for achieving high-performance 200MP sensors with a compact

👥 作者与机构

Richard Xu1, Guanjing Ren2, Yaowu Mo2, Dekui Qi2, Qian Wang2, Shengxin Zhang2

SmartSens Technology, Santa Clara, CA, 2SmartSens Technology, Shanghai, China