Chen-Kai Hsu1, Zhao Li6, Janet Brunsilius4, Enrique Alvarez-Fontecilla4, Robert Bishop1, Paul Wilkins1, Hassan L’Bahy1, Adalberto Cantoni1, Nuo Zhang1, Kaung Myat San Oo1, Cihan Asci1 Analog Devices, Wilmington, MA, 2Analog Devices, Austin, TX, 3Analog Devices, Durham, NC, 4Analog Devices, San Diego, CA, 5Analog Devices, Ottawa, Canada Analog Devices, Toronto, Canada 1 6 Abstract A 12b 12GS/s ADC with an integrated broadband RF VGA is implemented in a 5nm FinFET process. This combination achieves a programmable input range of 36dB from 250mVppd to 16Vppd, bandwidth of 8.5GHz, SNDR of 49dB, SFDR of 70dBc (with a 5.1GHz, -1dBFS input tone), and a single interleaving spur (<-90dBc) between DC and FS/2. Two pipelinestage architectures, “Flash Early-Trigger” and “Embedded SHA”, enable 6GS/s in a 12b sub-ADC, which is key to achieve two-way interleaving at 12GS/s. Wireless communication infrastructure demands highly integrated radio platforms. These
Haiyang Zhu1, Larry Singer1, Ron Kapusta1, Dan Kelly1, Tao Pan1, Mike Hensley2, Scott Bardsley3, Chris Dillon3, Daniel Rey-Losada4, Kashif M. Sheikh5,